On Thu, Aug 15, 2019 at 8:39 PM liuzhiwei <zhiwei_...@c-sky.com> wrote: > > Hi, Palmer > > When Michael Clark still was the maintainer of RISCV QEMU, he wrote in the > mail list, "the CLIC interrupt controller is under testing, > and will be included in QEMU 3.1 or 3.2". It is pity that the CLIC is not in > included even in QEMU 4.1.0.
I see that there is a CLIC branch available here: https://github.com/riscv/riscv-qemu/pull/157 It looks like all of the work is in a single commit (https://github.com/riscv/riscv-qemu/pull/157/commits/206d9ac339feb9ef2c325402a00f0f45f453d019) and that most of the other commits in the PR have already made it into master. Although the CLIC commit is very large it doesn't seem impossible to manually pull out the CLIC bits and apply it onto master. Do you know the state of the CLIC model? If it's working it shouldn't be too hard to rebase the work and get the code into mainline. Alistair > > As we have cpus using CLIC, I have to use the out of tree qemu code in SIFIVE > a long time. Could you tell me when it will be upstreamed? > > Best Regards > Zhiwei >
