Strawman version, WIP.
Signed-off-by: Blue Swirl <blauwir...@gmail.com>
---
tcg/i386/tcg-target.c | 6 ++++++
tcg/tcg-op.h | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
tcg/tcg-opc.h | 3 +++
3 files changed, 58 insertions(+), 0 deletions(-)
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index 8fc80af..b31e8bc 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -1676,6 +1676,9 @@ static inline void tcg_out_op(TCGContext *s,
TCGOpcode opc,
tcg_out_qemu_st(s, args, 3, TCG_AREG0);
break;
#endif
+ case INDEX_op_qemu_ld8u_new:
+ tcg_out_qemu_ld(s, args, 0, args[2]);
+ break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_brcond2_i32:
@@ -1860,6 +1863,7 @@ static const TCGTargetOpDef x86_op_defs[] = {
#if TCG_TARGET_REG_BITS == 64
{ INDEX_op_qemu_ld8u, { "r", "L" } },
+ { INDEX_op_qemu_ld8u_new, { "r", "L", "r" } },
{ INDEX_op_qemu_ld8s, { "r", "L" } },
{ INDEX_op_qemu_ld16u, { "r", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L" } },
@@ -1874,6 +1878,7 @@ static const TCGTargetOpDef x86_op_defs[] = {
{ INDEX_op_qemu_st64, { "L", "L" } },
#elif TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
{ INDEX_op_qemu_ld8u, { "r", "L" } },
+ { INDEX_op_qemu_ld8u_new, { "r", "L", "r" } },
{ INDEX_op_qemu_ld8s, { "r", "L" } },
{ INDEX_op_qemu_ld16u, { "r", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L" } },
@@ -1886,6 +1891,7 @@ static const TCGTargetOpDef x86_op_defs[] = {
{ INDEX_op_qemu_st64, { "L", "L", "L" } },
#else
{ INDEX_op_qemu_ld8u, { "r", "L", "L" } },
+ { INDEX_op_qemu_ld8u_new, { "r", "L", "L", "r" } },
{ INDEX_op_qemu_ld8s, { "r", "L", "L" } },
{ INDEX_op_qemu_ld16u, { "r", "L", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L", "L" } },
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 207a89f..eb62a06 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -141,6 +141,19 @@ static inline void
tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val,
*gen_opparam_ptr++ = mem_index;
}
+static inline void tcg_gen_qemu_ldst_op_new_i64_i32(TCGOpcode opc,
+ TCGv_i64 val,
+ TCGv_i32 addr,
+ TCGv_ptr r_cpustate,
+ TCGArg mem_index)
+{
+ *gen_opc_ptr++ = opc;
+ *gen_opparam_ptr++ = GET_TCGV_I64(val);
+ *gen_opparam_ptr++ = GET_TCGV_I32(addr);
+ *gen_opparam_ptr++ = GET_TCGV_PTR(r_cpustate);
+ *gen_opparam_ptr++ = mem_index;
+}
+
static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val,
TCGv_i64 addr, TCGArg
mem_index)
{
@@ -150,6 +163,19 @@ static inline void
tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val,
*gen_opparam_ptr++ = mem_index;
}
+static inline void tcg_gen_qemu_ldst_op_new_i64_i64(TCGOpcode opc,
+ TCGv_i64 val,
+ TCGv_i64 addr,
+ TCGv_ptr r_cpustate,
+ TCGArg mem_index)
+{
+ *gen_opc_ptr++ = opc;
+ *gen_opparam_ptr++ = GET_TCGV_I64(val);
+ *gen_opparam_ptr++ = GET_TCGV_I64(addr);
+ *gen_opparam_ptr++ = GET_TCGV_PTR(r_cpustate);
+ *gen_opparam_ptr++ = mem_index;
+}
+
static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
TCGv_i32 arg3, TCGv_i32 arg4)
{
@@ -2149,6 +2175,8 @@ static inline void tcg_gen_deposit_i64(TCGv_i64
ret, TCGv_i64 arg1,
#define tcg_temp_free tcg_temp_free_i32
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
+#define tcg_gen_qemu_ldst_op_new tcg_gen_op4i_i32
+#define tcg_gen_qemu_ldst_op_new_i64 tcg_gen_qemu_ldst_op_new_i64_i32
#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
#else
@@ -2160,6 +2188,8 @@ static inline void tcg_gen_deposit_i64(TCGv_i64
ret, TCGv_i64 arg1,
#define tcg_temp_free tcg_temp_free_i64
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
+#define tcg_gen_qemu_ldst_op_new tcg_gen_op4i_i64
+#define tcg_gen_qemu_ldst_op_new_i64 tcg_gen_qemu_ldst_op_new_i64_i64
#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
#endif
@@ -2198,6 +2228,18 @@ static inline void tcg_gen_qemu_ld8u(TCGv ret,
TCGv addr, int mem_index)
#endif
}
+static inline void tcg_gen_qemu_ld8u_new(TCGv ret, TCGv addr, TCGv r_cpustate,
+ int mem_index)
+{
+#if TARGET_LONG_BITS == 32
+ tcg_gen_op3i_i32(INDEX_op_qemu_ld8u_new, ret, addr, r_cpustate, mem_index);
+#else
+ tcg_gen_op4i_i32(INDEX_op_qemu_ld8u_new, TCGV_LOW(ret), TCGV_LOW(addr),
+ TCGV_HIGH(addr), r_cpustate, mem_index);
+ tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
+#endif
+}
+
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
{
#if TARGET_LONG_BITS == 32
@@ -2314,6 +2356,13 @@ static inline void tcg_gen_qemu_ld8u(TCGv ret,
TCGv addr, int mem_index)
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index);
}
+static inline void tcg_gen_qemu_ld8u_new(TCGv ret, TCGv addr, TCGv r_cpustate,
+ int mem_index)
+{
+ tcg_gen_qemu_ldst_op_new(INDEX_op_qemu_ld8u_new, ret, addr, r_cpustate,
+ mem_index);
+}
+
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
{
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index);
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 2c7ca1a..6660529 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -239,8 +239,10 @@ DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END |
TCG_OPF_SIDE_EFFECTS)
#if TCG_TARGET_REG_BITS == 32
#if TARGET_LONG_BITS == 32
DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
+DEF(qemu_ld8u_new, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
#else
DEF(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
+DEF(qemu_ld8u, 1, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
#endif
#if TARGET_LONG_BITS == 32
DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
@@ -292,6 +294,7 @@ DEF(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER |
TCG_OPF_SIDE_EFFECTS)
#else /* TCG_TARGET_REG_BITS == 32 */
DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
+DEF(qemu_ld8u_new, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
--
1.6.2.4
From 62d19f778b533fedef35d607dcfcdc9a4ca7d52e Mon Sep 17 00:00:00 2001
Message-Id: <62d19f778b533fedef35d607dcfcdc9a4ca7d52e.1305401750.git.blauwir...@gmail.com>
In-Reply-To: <6e21df8e369388a3152dcc7da30431c672e1ee37.1305401750.git.blauwir...@gmail.com>
References: <6e21df8e369388a3152dcc7da30431c672e1ee37.1305401750.git.blauwir...@gmail.com>
From: Blue Swirl <blauwir...@gmail.com>
Date: Sat, 14 May 2011 17:56:35 +0000
Subject: [PATCH 10/11] Add new qemu_ld and qemu_st functions
Strawman version, WIP.
Signed-off-by: Blue Swirl <blauwir...@gmail.com>
---
tcg/i386/tcg-target.c | 6 ++++++
tcg/tcg-op.h | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
tcg/tcg-opc.h | 3 +++
3 files changed, 58 insertions(+), 0 deletions(-)
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index 8fc80af..b31e8bc 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -1676,6 +1676,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_qemu_st(s, args, 3, TCG_AREG0);
break;
#endif
+ case INDEX_op_qemu_ld8u_new:
+ tcg_out_qemu_ld(s, args, 0, args[2]);
+ break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_brcond2_i32:
@@ -1860,6 +1863,7 @@ static const TCGTargetOpDef x86_op_defs[] = {
#if TCG_TARGET_REG_BITS == 64
{ INDEX_op_qemu_ld8u, { "r", "L" } },
+ { INDEX_op_qemu_ld8u_new, { "r", "L", "r" } },
{ INDEX_op_qemu_ld8s, { "r", "L" } },
{ INDEX_op_qemu_ld16u, { "r", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L" } },
@@ -1874,6 +1878,7 @@ static const TCGTargetOpDef x86_op_defs[] = {
{ INDEX_op_qemu_st64, { "L", "L" } },
#elif TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
{ INDEX_op_qemu_ld8u, { "r", "L" } },
+ { INDEX_op_qemu_ld8u_new, { "r", "L", "r" } },
{ INDEX_op_qemu_ld8s, { "r", "L" } },
{ INDEX_op_qemu_ld16u, { "r", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L" } },
@@ -1886,6 +1891,7 @@ static const TCGTargetOpDef x86_op_defs[] = {
{ INDEX_op_qemu_st64, { "L", "L", "L" } },
#else
{ INDEX_op_qemu_ld8u, { "r", "L", "L" } },
+ { INDEX_op_qemu_ld8u_new, { "r", "L", "L", "r" } },
{ INDEX_op_qemu_ld8s, { "r", "L", "L" } },
{ INDEX_op_qemu_ld16u, { "r", "L", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L", "L" } },
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 207a89f..eb62a06 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -141,6 +141,19 @@ static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val,
*gen_opparam_ptr++ = mem_index;
}
+static inline void tcg_gen_qemu_ldst_op_new_i64_i32(TCGOpcode opc,
+ TCGv_i64 val,
+ TCGv_i32 addr,
+ TCGv_ptr r_cpustate,
+ TCGArg mem_index)
+{
+ *gen_opc_ptr++ = opc;
+ *gen_opparam_ptr++ = GET_TCGV_I64(val);
+ *gen_opparam_ptr++ = GET_TCGV_I32(addr);
+ *gen_opparam_ptr++ = GET_TCGV_PTR(r_cpustate);
+ *gen_opparam_ptr++ = mem_index;
+}
+
static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val,
TCGv_i64 addr, TCGArg mem_index)
{
@@ -150,6 +163,19 @@ static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val,
*gen_opparam_ptr++ = mem_index;
}
+static inline void tcg_gen_qemu_ldst_op_new_i64_i64(TCGOpcode opc,
+ TCGv_i64 val,
+ TCGv_i64 addr,
+ TCGv_ptr r_cpustate,
+ TCGArg mem_index)
+{
+ *gen_opc_ptr++ = opc;
+ *gen_opparam_ptr++ = GET_TCGV_I64(val);
+ *gen_opparam_ptr++ = GET_TCGV_I64(addr);
+ *gen_opparam_ptr++ = GET_TCGV_PTR(r_cpustate);
+ *gen_opparam_ptr++ = mem_index;
+}
+
static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
TCGv_i32 arg3, TCGv_i32 arg4)
{
@@ -2149,6 +2175,8 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
#define tcg_temp_free tcg_temp_free_i32
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
+#define tcg_gen_qemu_ldst_op_new tcg_gen_op4i_i32
+#define tcg_gen_qemu_ldst_op_new_i64 tcg_gen_qemu_ldst_op_new_i64_i32
#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
#else
@@ -2160,6 +2188,8 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
#define tcg_temp_free tcg_temp_free_i64
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
+#define tcg_gen_qemu_ldst_op_new tcg_gen_op4i_i64
+#define tcg_gen_qemu_ldst_op_new_i64 tcg_gen_qemu_ldst_op_new_i64_i64
#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
#endif
@@ -2198,6 +2228,18 @@ static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
#endif
}
+static inline void tcg_gen_qemu_ld8u_new(TCGv ret, TCGv addr, TCGv r_cpustate,
+ int mem_index)
+{
+#if TARGET_LONG_BITS == 32
+ tcg_gen_op3i_i32(INDEX_op_qemu_ld8u_new, ret, addr, r_cpustate, mem_index);
+#else
+ tcg_gen_op4i_i32(INDEX_op_qemu_ld8u_new, TCGV_LOW(ret), TCGV_LOW(addr),
+ TCGV_HIGH(addr), r_cpustate, mem_index);
+ tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
+#endif
+}
+
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
{
#if TARGET_LONG_BITS == 32
@@ -2314,6 +2356,13 @@ static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index);
}
+static inline void tcg_gen_qemu_ld8u_new(TCGv ret, TCGv addr, TCGv r_cpustate,
+ int mem_index)
+{
+ tcg_gen_qemu_ldst_op_new(INDEX_op_qemu_ld8u_new, ret, addr, r_cpustate,
+ mem_index);
+}
+
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
{
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index);
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 2c7ca1a..6660529 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -239,8 +239,10 @@ DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
#if TCG_TARGET_REG_BITS == 32
#if TARGET_LONG_BITS == 32
DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
+DEF(qemu_ld8u_new, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
#else
DEF(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
+DEF(qemu_ld8u, 1, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
#endif
#if TARGET_LONG_BITS == 32
DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
@@ -292,6 +294,7 @@ DEF(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
#else /* TCG_TARGET_REG_BITS == 32 */
DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
+DEF(qemu_ld8u_new, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
--
1.7.2.5
