Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/arm/translate.c | 85 ++++++++++++++++++++----------------------
target/arm/t16.decode | 12 ++++++
2 files changed, 52 insertions(+), 45 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 414c562fb3..368f0ab147 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7474,6 +7474,11 @@ static int negate(DisasContext *s, int x)
return -x;
}
+static int plus_2(DisasContext *s, int x)
+{
+ return x + 2;
+}
+
static int times_2(DisasContext *s, int x)
{
return x * 2;
@@ -10152,6 +10157,9 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a)
{
uint32_t mask, val;
+ if (ENABLE_ARCH_6 && arm_dc_feature(s, ARM_FEATURE_M)) {
+ return false;
+ }
if (IS_USER(s)) {
/* Implemented as NOP in user mode. */
return true;
@@ -10182,6 +10190,36 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a)
return true;
}
+static bool trans_CPS_v6m(DisasContext *s, arg_CPS_v6m *a)
+{
+ TCGv_i32 tmp, addr;
+
+ if (!(ENABLE_ARCH_6 && arm_dc_feature(s, ARM_FEATURE_M))) {
+ return false;
+ }
+ if (IS_USER(s)) {
+ /* Implemented as NOP in user mode. */
+ return true;
+ }
+
+ tmp = tcg_const_i32(a->im);
+ /* FAULTMASK */
+ if (a->F) {
+ addr = tcg_const_i32(19);
+ gen_helper_v7m_msr(cpu_env, addr, tmp);
+ tcg_temp_free_i32(addr);
+ }
+ /* PRIMASK */
+ if (a->I) {
+ addr = tcg_const_i32(16);
+ gen_helper_v7m_msr(cpu_env, addr, tmp);
+ tcg_temp_free_i32(addr);
+ }
+ tcg_temp_free_i32(tmp);
+ gen_lookup_tb(s);
+ return true;
+}
+
/*
* Clear-Exclusive, Barriers
*/
@@ -10783,51 +10821,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
break;
}
- case 6:
- switch ((insn >> 5) & 7) {
- case 2:
- /* setend */
- ARCH(6);
- if (((insn >> 3) & 1) != !!(s->be_data == MO_BE)) {
- gen_helper_setend(cpu_env);
- s->base.is_jmp = DISAS_UPDATE;
- }
- break;
- case 3:
- /* cps */
- ARCH(6);
- if (IS_USER(s)) {
- break;
- }
- if (arm_dc_feature(s, ARM_FEATURE_M)) {
- tmp = tcg_const_i32((insn & (1 << 4)) != 0);
- /* FAULTMASK */
- if (insn & 1) {
- addr = tcg_const_i32(19);
- gen_helper_v7m_msr(cpu_env, addr, tmp);
- tcg_temp_free_i32(addr);
- }
- /* PRIMASK */
- if (insn & 2) {
- addr = tcg_const_i32(16);
- gen_helper_v7m_msr(cpu_env, addr, tmp);
- tcg_temp_free_i32(addr);
- }
- tcg_temp_free_i32(tmp);
- gen_lookup_tb(s);
- } else {
- if (insn & (1 << 4)) {
- shift = CPSR_A | CPSR_I | CPSR_F;
- } else {
- shift = 0;
- }
- gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
- }
- break;
- default:
- goto undef;
- }
- break;
+ case 6: /* setend, cps; in decodetree */
+ goto illegal_op;
default:
goto undef;
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index b5b5086e8a..3bf1a31731 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -29,6 +29,8 @@
&ldst_rr !extern p w u rn rt rm shimm shtype
&ldst_ri !extern p w u rn rt imm
&ldst_block !extern rn i b u w list
+&setend !extern E
+&cps !extern mode imod M A I F
# Set S if the instruction is outside of an IT block.
%s !function=t16_setflags
@@ -183,3 +185,13 @@ SXTAH 1011 0010 00 ... ... @extend
SXTAB 1011 0010 01 ... ... @extend
UXTAH 1011 0010 10 ... ... @extend
UXTAB 1011 0010 11 ... ... @extend
+
+# Change processor state
+
+%imod 4:1 !function=plus_2
+
+SETEND 1011 0110 010 1 E:1 000 &setend
+{
+ CPS_v6m 1011 0110 011 im:1 00 I:1 F:1
+ CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=0 M=0 %imod
+}
--
2.17.1
