On 08/22/19 08:18, Paolo Bonzini wrote: > On 21/08/19 22:17, Kinney, Michael D wrote: >> Paolo, >> >> It makes sense to match real HW. > > Note that it'd also be fine to match some kind of official Intel > specification even if no processor (currently?) supports it.
I agree, because... >> That puts us back to the reset vector and handling the initial SMI at >> 3000:8000. That is all workable from a FW implementation >> perspective. that would suggest that matching reset vector code already exists, and it would "only" need to be upstreamed to edk2. :) >> It look like the only issue left is DMA. >> >> DMA protection of memory ranges is a chipset feature. For the current >> QEMU implementation, what ranges of memory are guaranteed to be >> protected from DMA? Is it only A/B seg and TSEG? > > Yes. ( This thread (esp. Jiewen's and Mike's messages) are the first time that I've heard about the *existence* of such RAM ranges / the chipset feature. :) Out of interest (independently of virtualization), how is a general purpose OS informed by the firmware, "never try to set up DMA to this RAM area"? Is this communicated through ACPI _CRS perhaps? ... Ah, almost: ACPI 6.2 specifies _DMA, in "6.2.4 _DMA (Direct Memory Access)". It writes, For example, if a platform implements a PCI bus that cannot access all of physical memory, it has a _DMA object under that PCI bus that describes the ranges of physical memory that can be accessed by devices on that bus. Sorry about the digression, and also about being late to this thread, continually -- I'm primarily following and learning. ) Thanks! Laszlo