The first three fix an MTTCG race on cpu_R[0], now that we do code generation in parallel.
Then some updates to the SPRs, cpuid checks for existing float insns, adding the new v1.3 instructions. I've run this through the gcc testsuite as make check-gcc \ RUNTESTFLAGS='--target_board=or1k-qemu/-mhard-float/-mdouble-float execute.exp' === gcc Summary === # of expected passes 103979 # of unexpected failures 26 # of expected failures 400 # of unresolved testcases 1 # of unsupported tests 2539 Of the 26, none are obviously floating-point related. r~ Richard Henderson (13): target/openrisc: Add DisasContext parameter to check_r0_write target/openrisc: Replace cpu register array with a function target/openrisc: Cache R0 in DisasContext target/openrisc: Make VR and PPC read-only target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init target/openrisc: Add VR2 and AVR special processor registers target/openrisc: Fix lf.ftoi.s target/openrisc: Check CPUCFG_OF32S for float insns target/openrisc: Add support for ORFPX64A32 target/openrisc: Implement unordered fp comparisons target/openrisc: Implement move to/from FPCSR target/openrisc: Implement l.adrp target/openrisc: Update cpu "any" to v1.3 linux-user/openrisc/target_elf.h | 2 +- target/openrisc/cpu.h | 24 +- target/openrisc/helper.h | 6 + target/openrisc/cpu.c | 30 +- target/openrisc/disas.c | 81 ++++ target/openrisc/fpu_helper.c | 49 ++- target/openrisc/machine.c | 11 + target/openrisc/sys_helper.c | 38 +- target/openrisc/translate.c | 716 +++++++++++++++++++++++-------- target/openrisc/insns.decode | 45 ++ 10 files changed, 774 insertions(+), 228 deletions(-) -- 2.17.1