On Sun, 18 Aug 2019 at 07:12, Richard Henderson <richard.hender...@linaro.org> wrote: > > On 8/16/19 1:58 PM, Peter Maydell wrote: > > @@ -1729,6 +1729,12 @@ static void handle_sys(DisasContext *s, uint32_t > > insn, bool isread, > > tcg_temp_free_ptr(tmpptr); > > tcg_temp_free_i32(tcg_syn); > > tcg_temp_free_i32(tcg_isread); > > + } else if (ri->type & ARM_CP_RAISES_EXC) { > > + /* > > + * The readfn or writefn might raise an exception; > > + * synchronize the CPU state in case it does. > > + */ > > + gen_a64_set_pc_im(s->pc - 4); > > This will now need an update for master, but otherwise, > Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Thanks; applied series to target-arm.next with this squashed in to handle the changes in master: diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b3053d3fb89..4d09ae6f424 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1719,7 +1719,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, * The readfn or writefn might raise an exception; * synchronize the CPU state in case it does. */ - gen_a64_set_pc_im(s->pc - 4); + gen_a64_set_pc_im(s->pc_curr); } /* Handle special cases first */ diff --git a/target/arm/translate.c b/target/arm/translate.c index adb97dc6a3d..78d93f63cab 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7197,7 +7197,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) * synchronize the CPU state in case it does. */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->pc_curr); } /* Handle special cases first */ -- PMM