As for the other semihosting calls we can resolve this at translate
time.
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
---
target/arm/translate.c | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 6157e9f52fc..9dc7ec78061 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7657,6 +7657,22 @@ static void arm_skip_unless(DisasContext *s, uint32_t
cond)
arm_gen_test_cc(cond ^ 1, s->condlabel);
}
+static inline void gen_arm_swi(DisasContext *s, int imm24)
+{
+ if (semihosting_enabled() &&
+#ifndef CONFIG_USER_ONLY
+ s->current_el != 0 &&
+#endif
+ (imm24 == 0x123456)) {
+ gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
+ return;
+ }
+
+ gen_set_pc_im(s, s->base.pc_next);
+ s->svc_imm = imm24;
+ s->base.is_jmp = DISAS_SWI;
+}
+
static void disas_arm_insn(DisasContext *s, unsigned int insn)
{
unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh;
@@ -9195,9 +9211,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int
insn)
break;
case 0xf:
/* swi */
- gen_set_pc_im(s, s->base.pc_next);
- s->svc_imm = extract32(insn, 0, 24);
- s->base.is_jmp = DISAS_SWI;
+ gen_arm_swi(s, extract32(insn, 0, 24));
break;
default:
illegal_op:
--
2.20.1
