This unifies the implementation of the actual instructions for a32, t32, and t16.
There are a number of changes from v2, mostly from review feedback. I think that I've annotated them all via "v3:" tags after the commit, but I may have missed some. The patches without Reviewed-by are: 0019-target-arm-Convert-T32-ADDW-SUBW.patch 0022-target-arm-Diagnose-UNPREDICTABLE-ldrex-strex-cas.patch 0035-target-arm-Convert-Clear-Exclusive-Barriers.patch 0057-target-arm-Convert-T16-Change-processor-state.patch r~ Richard Henderson (69): target/arm: Use store_reg_from_load in thumb2 code target/arm: Add stubs for aa32 decodetree target/arm: Convert Data Processing (register) target/arm: Convert Data Processing (reg-shifted-reg) target/arm: Convert Data Processing (immediate) target/arm: Convert multiply and multiply accumulate target/arm: Simplify UMAAL target/arm: Convert Saturating addition and subtraction target/arm: Convert Halfword multiply and multiply accumulate target/arm: Simplify op_smlaxxx for SMLAL* target/arm: Simplify op_smlawx for SMLAW* target/arm: Convert MSR (immediate) and hints target/arm: Convert MRS/MSR (banked, register) target/arm: Convert Cyclic Redundancy Check target/arm: Convert BX, BXJ, BLX (register) target/arm: Convert CLZ target/arm: Convert ERET target/arm: Convert the rest of A32 Miscelaneous instructions target/arm: Convert T32 ADDW/SUBW target/arm: Convert load/store (register, immediate, literal) target/arm: Convert Synchronization primitives target/arm: Diagnose UNPREDICTABLE ldrex/strex cases target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF target/arm: Convert Parallel addition and subtraction target/arm: Convert packing, unpacking, saturation, and reversal target/arm: Convert Signed multiply, signed and unsigned divide target/arm: Convert MOVW, MOVT target/arm: Convert LDM, STM target/arm: Diagnose writeback register in list for LDM for v7 target/arm: Diagnose too few registers in list for LDM/STM target/arm: Diagnose base == pc for LDM/STM target/arm: Convert B, BL, BLX (immediate) target/arm: Convert SVC target/arm: Convert RFE and SRS target/arm: Convert Clear-Exclusive, Barriers target/arm: Convert CPS (privileged) target/arm: Convert SETEND target/arm: Convert PLI, PLD, PLDW target/arm: Convert Unallocated memory hint target/arm: Convert Table Branch target/arm: Convert SG target/arm: Convert TT target/arm: Simplify disas_thumb2_insn target/arm: Simplify disas_arm_insn target/arm: Add skeleton for T16 decodetree target/arm: Convert T16 data-processing (two low regs) target/arm: Convert T16 load/store (register offset) target/arm: Convert T16 load/store (immediate offset) target/arm: Convert T16 add pc/sp (immediate) target/arm: Convert T16 load/store multiple target/arm: Convert T16 add/sub (3 low, 2 low and imm) target/arm: Convert T16 one low register and immediate target/arm: Convert T16 branch and exchange target/arm: Convert T16 add, compare, move (two high registers) target/arm: Convert T16 adjust sp (immediate) target/arm: Convert T16, extract target/arm: Convert T16, Change processor state target/arm: Convert T16, Reverse bytes target/arm: Convert T16, nop hints target/arm: Split gen_nop_hint target/arm: Convert T16, push and pop target/arm: Convert T16, Conditional branches, Supervisor call target/arm: Convert T16, Miscellaneous 16-bit instructions target/arm: Convert T16, shift immediate target/arm: Convert T16, load (literal) target/arm: Convert T16, Unconditional branch target/arm: Convert T16, long branches target/arm: Clean up disas_thumb_insn target/arm: Inline gen_bx_im into callers target/arm/translate.c | 7166 +++++++++++++++------------------- target/arm/Makefile.objs | 24 + target/arm/a32-uncond.decode | 74 + target/arm/a32.decode | 534 +++ target/arm/t16.decode | 281 ++ target/arm/t32.decode | 631 +++ 6 files changed, 4641 insertions(+), 4069 deletions(-) create mode 100644 target/arm/a32-uncond.decode create mode 100644 target/arm/a32.decode create mode 100644 target/arm/t16.decode create mode 100644 target/arm/t32.decode -- 2.17.1
