On 9/12/19 8:54 AM, Paul A. Clarke wrote: > From: "Paul A. Clarke" <p...@us.ibm.com> > > ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR) > instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl. > This patch adds support for 'mffsce' instruction. > > 'mffsce' is identical to 'mffs', except that it also clears the exception > enable bits in the FPSCR. > > On CPUs without support for 'mffsce' (below ISA 3.0), the > instruction will execute identically to 'mffs'. > > Signed-off-by: Paul A. Clarke <p...@us.ibm.com> > --- > target/ppc/translate/fp-impl.inc.c | 30 ++++++++++++++++++++++++++++++ > target/ppc/translate/fp-ops.inc.c | 2 ++ > 2 files changed, 32 insertions(+) > > diff --git a/target/ppc/translate/fp-impl.inc.c > b/target/ppc/translate/fp-impl.inc.c > index 59a4faf..34edc45 100644 > --- a/target/ppc/translate/fp-impl.inc.c > +++ b/target/ppc/translate/fp-impl.inc.c > @@ -639,6 +639,36 @@ static void gen_mffsl(DisasContext *ctx) > tcg_temp_free_i64(t0); > } > > +/* mffsce */ > +static void gen_mffsce(DisasContext *ctx) > +{ > + TCGv_i64 t0; > + TCGv_i32 mask; > + > + if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { > + return gen_mffs(ctx); > + } > + > + if (unlikely(!ctx->fpu_enabled)) { > + gen_exception(ctx, POWERPC_EXCP_FPU); > + return; > + } > + > + t0 = tcg_temp_new_i64(); > + > + gen_reset_fpstatus();
Note for future cleanup: we should not need to sprinkle these all over. This should be the steady-state condition after softfp exceptions have been processed into powerpc exceptions, after every single fp instruction. That said, you're mirroring gen_mffs here, and the cleanup should happen globally. Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~