On 9/18/19 1:23 AM, Alistair Francis wrote:
> From: Palmer Dabbelt <pal...@sifive.com>
>
> This converts our port over from cpu_do_unassigned_access to
> cpu_do_transaction_failed, as cpu_do_unassigned_access has been
> deprecated.
>
> Signed-off-by: Palmer Dabbelt <pal...@sifive.com>
> Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
> ---
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu.h | 7 +++++--
> target/riscv/cpu_helper.c | 11 +++++++----
> 3 files changed, 13 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index f13e298a36..3939963b71 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -484,7 +484,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void
> *data)
> cc->gdb_stop_before_watchpoint = true;
> cc->disas_set_info = riscv_cpu_disas_set_info;
> #ifndef CONFIG_USER_ONLY
> - cc->do_unassigned_access = riscv_cpu_unassigned_access;
> + cc->do_transaction_failed = riscv_cpu_do_transaction_failed;
> cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
> cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
> #endif
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 124ed33ee4..8c64c68538 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -264,8 +264,11 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr
> addr,
> bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> MMUAccessType access_type, int mmu_idx,
> bool probe, uintptr_t retaddr);
> -void riscv_cpu_unassigned_access(CPUState *cpu, hwaddr addr, bool is_write,
> - bool is_exec, int unused, unsigned size);
> +void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
> + vaddr addr, unsigned size,
> + MMUAccessType access_type,
> + int mmu_idx, MemTxAttrs attrs,
> + MemTxResult response, uintptr_t
> retaddr);
> char *riscv_isa_string(RISCVCPU *cpu);
> void riscv_cpu_list(void);
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index c82e7ed52b..917252f71b 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -408,20 +408,23 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs,
> vaddr addr)
> return phys_addr;
> }
>
> -void riscv_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write,
> - bool is_exec, int unused, unsigned size)
> +void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
> + vaddr addr, unsigned size,
> + MMUAccessType access_type,
> + int mmu_idx, MemTxAttrs attrs,
> + MemTxResult response, uintptr_t retaddr)
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
>
> - if (is_write) {
> + if (access_type == MMU_DATA_STORE) {
> cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
> } else {
> cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
> }
>
> env->badaddr = addr;
> - riscv_raise_exception(&cpu->env, cs->exception_index, GETPC());
> + riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
> }
>
> void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>
Reviewed-by: Philippe Mathieu-Daudé <phi...@redhat.com>
