Perform constant folding for AND, OR, XOR operations. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/optimize.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 58 insertions(+), 0 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c index 4073f05..a02d5c1 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -38,6 +38,13 @@ typedef enum { TCG_TEMP_ANY } tcg_temp_state; +const int mov_opc[] = { + INDEX_op_mov_i32, +#if TCG_TARGET_REG_BITS == 64 + INDEX_op_mov_i64, +#endif +}; + static int mov_to_movi(int op) { switch (op) { @@ -89,12 +96,18 @@ static int op_bits(int op) case INDEX_op_add_i32: case INDEX_op_sub_i32: case INDEX_op_mul_i32: + case INDEX_op_and_i32: + case INDEX_op_or_i32: + case INDEX_op_xor_i32: return 32; #if TCG_TARGET_REG_BITS == 64 case INDEX_op_mov_i64: case INDEX_op_add_i64: case INDEX_op_sub_i64: case INDEX_op_mul_i64: + case INDEX_op_and_i64: + case INDEX_op_or_i64: + case INDEX_op_xor_i64: return 64; #endif default: @@ -137,6 +150,24 @@ static TCGArg do_constant_folding_2(int op, TCGArg x, TCGArg y) #endif return x * y; + case INDEX_op_and_i32: +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_and_i64: +#endif + return x & y; + + case INDEX_op_or_i32: +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_or_i64: +#endif + return x | y; + + case INDEX_op_xor_i32: +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_xor_i64: +#endif + return x ^ y; + default: fprintf(stderr, "Unrecognized operation %d in do_constant_folding.\n", op); @@ -237,10 +268,37 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, gen_args += 2; args += 2; break; + case INDEX_op_or_i32: + case INDEX_op_and_i32: +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_and_i64: + case INDEX_op_or_i64: +#endif + if (args[1] == args[2]) { + if (args[1] == args[0]) { + args += 3; + gen_opc_buf[op_index] = INDEX_op_nop; + } else { + reset_temp(state, vals, args[0], nb_temps, nb_globals); + if (args[1] >= s->nb_globals) { + state[args[0]] = TCG_TEMP_COPY; + vals[args[0]] = args[1]; + } + gen_opc_buf[op_index] = mov_opc[op_bits(op) / 32 - 1]; + gen_args[0] = args[0]; + gen_args[1] = args[1]; + gen_args += 2; + args += 3; + } + break; + } + /* Proceed with default binary operation handling */ + case INDEX_op_xor_i32: case INDEX_op_add_i32: case INDEX_op_sub_i32: case INDEX_op_mul_i32: #if TCG_TARGET_REG_BITS == 64 + case INDEX_op_xor_i64: case INDEX_op_add_i64: case INDEX_op_sub_i64: case INDEX_op_mul_i64: -- 1.7.4.1