Hello, The Aspeed I2C controller can operate in three different transfer modes :
- Byte Buffer mode, using a dedicated register to transfer a byte. This is what the model supports today. - Pool Buffer mode, using an internal SRAM to transfer multiple bytes in the same command sequence. - DMA mode, supporting transfers up to 4K to and from DRAM. This series adds support for the pool and DMA transfer modes taking into account the specificities of each SoC. Last patch adds some traces which proved to be useful to debug the I2C state machine. Thanks, C. Cédric Le Goater (5): aspeed/i2c: Add support for pool buffer transfers aspeed/i2c: Check SRAM enablement on A2500 aspeed: Add a DRAM memory region at the SoC level aspeed/i2c: Add support for DMA transfers aspeed/i2c: Add trace events include/hw/arm/aspeed_soc.h | 1 + include/hw/i2c/aspeed_i2c.h | 16 ++ hw/arm/aspeed_ast2600.c | 12 +- hw/arm/aspeed_soc.c | 14 +- hw/i2c/aspeed_i2c.c | 439 +++++++++++++++++++++++++++++++++--- hw/i2c/trace-events | 9 + 6 files changed, 459 insertions(+), 32 deletions(-) -- 2.21.0