On 10/16/2019 1:50 AM, Cédric Le Goater wrote:
The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA
transfers to and from DRAM.
A pair of registers defines the buffer address and the length of the
DMA transfer. The address should be aligned on 4 bytes and the maximum
length should not exceed 4K. The receive or transmit DMA transfer can
then be initiated with specific bits in the Command/Status register of
the controller.
Signed-off-by: Cédric Le Goater <c...@kaod.org>
Tested-by: Jae Hyun Yoo <jae.hyun....@linux.intel.com>
