On Tue, 24 May 2011, Laurent Desnogues wrote:
> On Tue, May 24, 2011 at 1:31 PM, Kirill Batuzov <batuz...@ispras.ru> wrote: > [...] > > Gathered statistics shows some interesting things too. I've run matrix > > multiplication benchmark (guest - ARM, host - x86, linux-user mode, with > > my patches applied) and here are the results: > > > > spill count 3916 > > real spills 32 > > spills at bb end 1023 > > spills at call: > > globals 2755 > > iarg passing 0 > > call cloobers 106 > > > > Real spills are spills generated by register allocator when it runs out > > of registers. They are less than 1% of all spills. Other tests show > > similar behavior. > > When you write "host x86", do you mean IA32 or x86_64? > That might change the number of real spills a lot if you meant > x86_64. > I mean IA32, not x86_64. > > I think any further improvements to register allocator without leveling > > conventions about saving globals at calls and BB ends somehow is > > useless. > > > > Currently we are looking if we can pass some globals on registers > > through basic block boundaries (inside one TB of course). > > If by "basic block", you mean BB as implied by TCG br for > instance, I'm not sure all guests will benefit a lot. If you > mean that you intend on putting several guests BB in a > single TB then I guess you'll have to first collect dynamic > statistics before dynamically switching to grouping BB. > I mean BB as implied by TCG br. Even if only some guest will benefit from this it still looks like a good idea. Other guests should not be affected much I believe. ---- Kirill.
