On Thu, 26 May 2011, Brad wrote:
> ----- Original message -----
> > On Wed, 25 May 2011, Brad wrote:
> >
> > > Add ppc_init_cacheline_sizes() function for OpenBSD to fix compilation
> > > of PowerPC host support for OpenBSD/powerpc based architectures.
> > >
> > > Signed-off-by: Brad Smith <b...@comstyle.com>
> > >
> > > ---
> > > cache-utils.c | 11 +++++++++--
> > > 1 files changed, 9 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/cache-utils.c b/cache-utils.c
> > > index 2db5af2..c319705 100644
> > > --- a/cache-utils.c
> > > +++ b/cache-utils.c
> > > @@ -55,9 +55,16 @@ static void ppc_init_cacheline_sizes(void)
> > > qemu_cache_conf.icache_bsize = cacheline;
> > > }
> > > }
> > > -#endif
> > >
> > > -#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
> > > +#elif defined(__OpenBSD__)
> > > +
> > > +static void ppc_init_cacheline_sizes(void)
> > > +{
> > > + qemu_cache_conf.dcache_bsize = 32;
> > > + qemu_cache_conf.icache_bsize = 32;
> > > +}
> > > +
> > > +#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
> > > #include <errno.h>
> > > #include <stdio.h>
> > > #include <stdlib.h>
> > >
> >
> > This can't be right for most ppc64's.
>
> Well this is what OpenBSD currently does and runs on G5's in 32-bit mode only.
>
Mode of operation does not, to the best of my knowledge, change the
hardware limits, the cache line size will still be 128 on those G5s.
--
mailto:av1...@comtv.ru
