On Tue, 12 Nov 2019 at 11:57, Peter Maydell <peter.mayd...@linaro.org> wrote: > On Tue, 12 Nov 2019 at 07:28, Alexander Graf <g...@amazon.com> wrote: > > I still think that being consistent with the actual PL031 spec is > > preferable though. If any real world guest breaks because of this, we > > can still revert this patch and document the exact breakage in the > > comment instead. > > Yeah, I agree; I'm essentially just gathering material > for the commit message here. (The gold standard would be > to go find some hardware with a real pl031 and prod it > to confirm behaviour, but that's more effort than really > seems justified to me.)
I propose to put this in for 4.2 with an updated commit message: ===begin=== pl031: Expose RTCICR as proper WC register The current PL031 RTCICR register implementation always clears the IRQ pending status on a register write, regardless of the value the guest writes. To justify that behavior, it references the ARM926EJ-S Development Chip Reference Manual (DDI0287B) and indicates that said document states that any write clears the internal IRQ state. It is indeed true that in section 11.1 this document says: "The interrupt is cleared by writing any data value to the interrupt clear register RTCICR". However, later in section 11.2.2 it contradicts itself by saying: "Writing 1 to bit 0 of RTCICR clears the RTCINTR flag." The latter statement matches the PL031 TRM (DDI0224C), which says: "Writing 1 to bit position 0 clears the corresponding interrupt. Writing 0 has no effect." Let's assume that the self-contradictory DDI0287B is in error, and follow the reference manual for the device itself, by making the register write-one-to-clear. ===endit=== Is that OK? thanks -- PMM