When doing CAM line compares, fetch the block id from the interrupt
controller which can have set the PC_TCTXT_CHIPID field.
Signed-off-by: Cédric Le Goater <c...@kaod.org>
---
include/hw/ppc/xive.h | 2 +-
hw/intc/pnv_xive.c | 6 ++++++
hw/intc/spapr_xive.c | 6 ++++++
hw/intc/xive.c | 21 ++++++++++++++++-----
4 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 9c0bf2c301e2..1b7b89098f71 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -351,6 +351,7 @@ typedef struct XiveRouterClass {
XiveNVT *nvt);
int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt, uint8_t word_number);
+ uint8_t (*get_block_id)(XiveRouter *xrtr);
} XiveRouterClass;
int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
@@ -431,7 +432,6 @@ typedef struct XiveENDSource {
DeviceState parent;
uint32_t nr_ends;
- uint8_t block_id;
/* ESB memory region */
uint32_t esb_shift;
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 93c27cce568b..c7c2fe3a7b5f 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -466,6 +466,11 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t
format,
return count;
}
+static uint8_t pnv_xive_get_block_id(XiveRouter *xrtr)
+{
+ return pnv_xive_block_id(PNV_XIVE(xrtr));
+}
+
/*
* The TIMA MMIO space is shared among the chips and to identify the
* chip from which the access is being done, we extract the chip id
@@ -1926,6 +1931,7 @@ static void pnv_xive_class_init(ObjectClass *klass, void
*data)
xrc->write_end = pnv_xive_write_end;
xrc->get_nvt = pnv_xive_get_nvt;
xrc->write_nvt = pnv_xive_write_nvt;
+ xrc->get_block_id = pnv_xive_get_block_id;
xnc->notify = pnv_xive_notify;
xpc->match_nvt = pnv_xive_match_nvt;
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 1542cef91878..daa0656859a3 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -473,6 +473,11 @@ static int spapr_xive_match_nvt(XivePresenter *xptr,
uint8_t format,
return count;
}
+static uint8_t spapr_xive_get_block_id(XiveRouter *xrtr)
+{
+ return SPAPR_XIVE_BLOCK_ID;
+}
+
static const VMStateDescription vmstate_spapr_xive_end = {
.name = TYPE_SPAPR_XIVE "/end",
.version_id = 1,
@@ -764,6 +769,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void
*data)
xrc->write_end = spapr_xive_write_end;
xrc->get_nvt = spapr_xive_get_nvt;
xrc->write_nvt = spapr_xive_write_nvt;
+ xrc->get_block_id = spapr_xive_get_block_id;
sicc->activate = spapr_xive_activate;
sicc->deactivate = spapr_xive_deactivate;
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index ce904b0b5ab4..e5159466f088 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1371,17 +1371,25 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t
nvt_blk, uint32_t nvt_idx,
return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number);
}
+static int xive_router_get_block_id(XiveRouter *xrtr)
+{
+ XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
+
+ return xrc->get_block_id(xrtr);
+}
+
/*
* Encode the HW CAM line in the block group mode format :
*
* chip << 19 | 0000000 0 0001 thread (7Bit)
*/
-static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx)
+static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx)
{
CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
uint32_t pir = env->spr_cb[SPR_PIR].default_value;
+ uint8_t blk = xive_router_get_block_id(XIVE_ROUTER(xptr));
- return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f));
+ return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f));
}
/*
@@ -1418,7 +1426,7 @@ int xive_presenter_tctx_match(XivePresenter *xptr,
XiveTCTX *tctx,
/* PHYS ring */
if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) &&
- cam == xive_tctx_hw_cam_line(tctx)) {
+ cam == xive_tctx_hw_cam_line(xptr, tctx)) {
return TM_QW3_HV_PHYS;
}
@@ -1755,7 +1763,11 @@ static uint64_t xive_end_source_read(void *opaque,
hwaddr addr, unsigned size)
uint8_t pq;
uint64_t ret = -1;
- end_blk = xsrc->block_id;
+ /*
+ * The block id should be deduced from the load address on the END
+ * ESB MMIO but our model only supports a single block per XIVE chip.
+ */
+ end_blk = xive_router_get_block_id(xsrc->xrtr);
end_idx = addr >> (xsrc->esb_shift + 1);
if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) {
@@ -1855,7 +1867,6 @@ static void xive_end_source_realize(DeviceState *dev,
Error **errp)
}
static Property xive_end_source_properties[] = {
- DEFINE_PROP_UINT8("block-id", XiveENDSource, block_id, 0),
DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0),
DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K),
DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER,
--
2.21.0
