From: "Qi, Yadong" <yadong...@intel.com> The following patches are to refine/fix issues of reserved fields checking logic of Second-Level Paging Entries of VT-d: - split the resevred fields arrays into two ones, - large page only effect for L2(2M) and L3(1G), so remove checking of L1 and L4 for large page, - when dt is supported, TM filed should not be Reserved(0).
Changes in v3: - large page only effect for L2(2M) and L3(1G), so remove checking of L1 and L4 for large page Qi, Yadong (2): intel_iommu: refine SL-PEs reserved fields checking intel_iommu: TM field should not be in reserved bits hw/i386/intel_iommu.c | 40 +++++++++++++++++++--------------- hw/i386/intel_iommu_internal.h | 18 +++++++++------ 2 files changed, 34 insertions(+), 24 deletions(-) -- 2.17.1
