On 12/2/19 4:34 PM, Peter Maydell wrote:
> On Wed, 4 Sep 2019 at 13:56, Damien Hedde <damien.he...@greensocs.com> wrote:
>>
>> Add the connection between the slcr's output clocks and the uarts inputs.
>>
>> Also add the main board clock 'ps_clk', which is hard-coded to 33.33MHz
>> (the default frequency). This clock is used to feed the slcr's input
>> clock.
>>
>> Signed-off-by: Damien Hedde <damien.he...@greensocs.com>
>
> Nothing obviously wrong in the body of the patch, but as with
> 7 and 8, review from a Xilinx person would be helpful.
>
> /* board base frequency: 33.333333 MHz */
> #define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3)
>
> This is interesting, because it's not an integer... I'll come back
> to this topic in a reply to the cover letter in a moment.
For this precise case, what I wanted is the resulting integer which I
got from the device trees in linux (btw I should probably add this point
in comment). Just thought it was more readable this way than "33333333".
--
Damien
