Hi Simon, On 12/16/19 4:15 PM, Simon Veith wrote: > There are two issues with the current value of SMMU_BASE_ADDR_MASK: > > - At the lower end, we are clearing bits [4:0]. Per the SMMUv3 spec, > we should also be treating bit 5 as zero in the base address. > - At the upper end, we are clearing bits [63:48]. Per the SMMUv3 spec, > only bits [63:52] must be explicitly treated as zero. > > Update the SMMU_BASE_ADDR_MASK value to mask out bits [63:52] and [5:0]. > > ref. ARM IHI 0070C, section 6.3.23. > > Signed-off-by: Simon Veith <sve...@amazon.de> > Cc: Eric Auger <eric.au...@redhat.com> > Cc: qemu-devel@nongnu.org > Cc: qemu-...@nongnu.org Acked-by: Eric Auger <eric.au...@redhat.com>
Thanks Eric > --- > hw/arm/smmuv3-internal.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index d190181..042b435 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -99,7 +99,7 @@ REG32(GERROR_IRQ_CFG2, 0x74) > > #define A_STRTAB_BASE 0x80 /* 64b */ > > -#define SMMU_BASE_ADDR_MASK 0xffffffffffe0 > +#define SMMU_BASE_ADDR_MASK 0xfffffffffffc0 > > REG32(STRTAB_BASE_CFG, 0x88) > FIELD(STRTAB_BASE_CFG, FMT, 16, 2) >
