On 1/31/20 5:11 AM, Peter Maydell wrote: >> { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, >> .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, >> - .access = PL2_RW, >> - /* no .writefn needed as this can't cause an ASID change; >> - * no .raw_writefn or .resetfn needed as we never use mask/base_mask >> - */ >> + .access = PL2_RW, .writefn = vmsa_tcr_el12_write, > > This blows away the entire TLB on a TCR_EL2 write, which is > safe but a bit overzealous; we could skip it if E2H was clear > (and probably also be a bit more precise about which TLB > indexes to clear). But it's not a big deal so I'm happy if > we leave this as-is.
Yes, it is overzealous. I once had a patch set that attempted to track actual ASID changes and also contained the set of tlb indexes to clear. I thought about incorporating that here, but decided against. r~