On 2/11/20 9:37 AM, Peter Maydell wrote: > The ARMv8.4-PMU extension adds: > * one new required event, STALL > * one new system register PMMIR_EL1 > > (There are also some more L1-cache related events, but since > we don't implement any cache we don't provide these, in the > same way we don't provide the base-PMUv3 cache events.) > > The STALL event "counts every attributable cycle on which no > attributable instruction or operation was sent for execution on this > PE". QEMU doesn't stall in this sense, so this is another > always-reads-zero event. > > The PMMIR_EL1 register is a read-only register providing > implementation-specific information about the PMU; currently it has > only one field, SLOTS, which defines behaviour of the STALL_SLOT PMU > event. Since QEMU doesn't implement the STALL_SLOT event, we can > validly make the register read zero. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target/arm/cpu.h | 18 ++++++++++++++++++ > target/arm/helper.c | 22 +++++++++++++++++++++- > 2 files changed, 39 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
