Public bug reported:
On 32-bit and 64-bit ARM platforms, setting HCR.TSW is supposed to "Trap
data or unified cache maintenance instructions that operate by Set/Way."
Quoting the ARM manual:
If EL1 is using AArch64 state, accesses to DC ISW, DC CSW, DC CISW are trapped
to EL2, reported using EC syndrome value 0x18.
If EL1 is using AArch32 state, accesses to DCISW, DCCSW, DCCISW are trapped to
EL2, reported using EC syndrome value 0x03.
However, QEMU does not trap those instructions/registers. This was
tested on the branch master of the git repo.
** Affects: qemu
Importance: Undecided
Status: New
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https://bugs.launchpad.net/bugs/1863685
Title:
ARM: HCR.TSW traps are not implemented
Status in QEMU:
New
Bug description:
On 32-bit and 64-bit ARM platforms, setting HCR.TSW is supposed to
"Trap data or unified cache maintenance instructions that operate by
Set/Way." Quoting the ARM manual:
If EL1 is using AArch64 state, accesses to DC ISW, DC CSW, DC CISW are
trapped to EL2, reported using EC syndrome value 0x18.
If EL1 is using AArch32 state, accesses to DCISW, DCCSW, DCCISW are trapped
to EL2, reported using EC syndrome value 0x03.
However, QEMU does not trap those instructions/registers. This was
tested on the branch master of the git repo.
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