On Thu, 13 Feb 2020 12:17:18 -0600 Babu Moger <babu.mo...@amd.com> wrote:
> These functions add support for building EPYC mode topology given the smp > details like numa nodes, cores, threads and sockets. > > The new apic id decoding is mostly similar to current apic id decoding > except that it adds a new field llc_id when numa configured. Removes all llc_id/nodes_per_pkg > the hardcoded values. Subsequent patches will use these functions to build > the topology. > > Following functions are added. > apicid_llc_width_epyc > apicid_llc_offset_epyc > apicid_pkg_offset_epyc > apicid_from_topo_ids_epyc > x86_topo_ids_from_idx_epyc > x86_topo_ids_from_apicid_epyc > x86_apicid_from_cpu_idx_epyc > > The topology details are available in Processor Programming Reference (PPR) > for AMD Family 17h Model 01h, Revision B1 Processors. > https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip also checkpatch doesn't like this patch for too long strings. with that fixed Acked-by: Igor Mammedov <imamm...@redhat.com> PS: similar checkpatch warnings should be fixed in preceding patches > > Signed-off-by: Babu Moger <babu.mo...@amd.com> > --- > include/hw/i386/topology.h | 93 > ++++++++++++++++++++++++++++++++++++++++++++ > include/hw/i386/x86.h | 1 > 2 files changed, 94 insertions(+) > > diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h > index 3158157430..d9319dc2ac 100644 > --- a/include/hw/i386/topology.h > +++ b/include/hw/i386/topology.h > @@ -83,6 +83,11 @@ static inline unsigned apicid_die_width(X86CPUTopoInfo > *topo_info) > return apicid_bitwidth_for_count(topo_info->dies_per_pkg); > } > > +/* Bit width of the node_id field per socket */ > +static inline unsigned apicid_node_width_epyc(X86CPUTopoInfo *topo_info) > +{ > + return apicid_bitwidth_for_count(MAX(topo_info->nodes_per_pkg, 1)); > +} > /* Bit offset of the Core_ID field > */ > static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info) > @@ -103,6 +108,94 @@ static inline unsigned apicid_pkg_offset(X86CPUTopoInfo > *topo_info) > return apicid_die_offset(topo_info) + apicid_die_width(topo_info); > } > > +#define LLC_OFFSET 3 /* Minimum LLC offset if numa configured */ > + > +/* Bit offset of the node_id field */ > +static inline unsigned apicid_node_offset_epyc(X86CPUTopoInfo *topo_info) > +{ > + unsigned offset = apicid_die_offset(topo_info) + > + apicid_die_width(topo_info); > + > + if (topo_info->nodes_per_pkg) { > + return MAX(LLC_OFFSET, offset); > + } else { > + return offset; > + } > +} > + > +/* Bit offset of the Pkg_ID (socket ID) field */ > +static inline unsigned apicid_pkg_offset_epyc(X86CPUTopoInfo *topo_info) > +{ > + return apicid_node_offset_epyc(topo_info) + > apicid_node_width_epyc(topo_info); > +} > + > +/* > + * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID > + * > + * The caller must make sure core_id < nr_cores and smt_id < nr_threads. > + */ > +static inline apic_id_t x86_apicid_from_topo_ids_epyc(X86CPUTopoInfo > *topo_info, > + const X86CPUTopoIDs > *topo_ids) > +{ > + return (topo_ids->pkg_id << apicid_pkg_offset_epyc(topo_info)) | > + (topo_ids->node_id << apicid_node_offset_epyc(topo_info)) | > + (topo_ids->die_id << apicid_die_offset(topo_info)) | > + (topo_ids->core_id << apicid_core_offset(topo_info)) | > + topo_ids->smt_id; > +} > + > +static inline void x86_topo_ids_from_idx_epyc(X86CPUTopoInfo *topo_info, > + unsigned cpu_index, > + X86CPUTopoIDs *topo_ids) > +{ > + unsigned nr_nodes = MAX(topo_info->nodes_per_pkg, 1); > + unsigned nr_dies = topo_info->dies_per_pkg; > + unsigned nr_cores = topo_info->cores_per_die; > + unsigned nr_threads = topo_info->threads_per_core; > + unsigned cores_per_node = DIV_ROUND_UP((nr_dies * nr_cores * nr_threads), > + nr_nodes); > + > + topo_ids->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads); > + topo_ids->node_id = (cpu_index / cores_per_node) % nr_nodes; > + topo_ids->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies; > + topo_ids->core_id = cpu_index / nr_threads % nr_cores; > + topo_ids->smt_id = cpu_index % nr_threads; > +} > + > +/* > + * Calculate thread/core/package IDs for a specific topology, > + * based on APIC ID > + */ > +static inline void x86_topo_ids_from_apicid_epyc(apic_id_t apicid, > + X86CPUTopoInfo *topo_info, > + X86CPUTopoIDs *topo_ids) > +{ > + topo_ids->smt_id = apicid & > + ~(0xFFFFFFFFUL << apicid_smt_width(topo_info)); > + topo_ids->core_id = > + (apicid >> apicid_core_offset(topo_info)) & > + ~(0xFFFFFFFFUL << apicid_core_width(topo_info)); > + topo_ids->die_id = > + (apicid >> apicid_die_offset(topo_info)) & > + ~(0xFFFFFFFFUL << apicid_die_width(topo_info)); > + topo_ids->node_id = > + (apicid >> apicid_node_offset_epyc(topo_info)) & > + ~(0xFFFFFFFFUL << apicid_node_width_epyc(topo_info)); > + topo_ids->pkg_id = apicid >> apicid_pkg_offset_epyc(topo_info); > +} > + > +/* > + * Make APIC ID for the CPU 'cpu_index' > + * > + * 'cpu_index' is a sequential, contiguous ID for the CPU. > + */ > +static inline apic_id_t x86_apicid_from_cpu_idx_epyc(X86CPUTopoInfo > *topo_info, > + unsigned cpu_index) > +{ > + X86CPUTopoIDs topo_ids; > + x86_topo_ids_from_idx_epyc(topo_info, cpu_index, &topo_ids); > + return x86_apicid_from_topo_ids_epyc(topo_info, &topo_ids); > +} > /* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID > * > * The caller must make sure core_id < nr_cores and smt_id < nr_threads. > diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h > index d76fd0bbb1..38c2d27910 100644 > --- a/include/hw/i386/x86.h > +++ b/include/hw/i386/x86.h > @@ -42,6 +42,7 @@ typedef uint32_t apic_id_t; > > typedef struct X86CPUTopoIDs { > unsigned pkg_id; > + unsigned node_id; > unsigned die_id; > unsigned core_id; > unsigned smt_id; >