On Fri, Feb 21, 2020 at 1:45 AM LIU Zhiwei <zhiwei_...@c-sky.com> wrote:
>
> vlen is the vector register length in bits.
> elen is the max element size in bits.
> vext_spec is the vector specification version, default value is v0.7.1.
>
> Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 7 +++++++
> target/riscv/cpu.h | 5 +++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 8c86ebc109..6900714432 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -98,6 +98,11 @@ static void set_priv_version(CPURISCVState *env, int
> priv_ver)
> env->priv_ver = priv_ver;
> }
>
> +static void set_vext_version(CPURISCVState *env, int vext_ver)
> +{
> + env->vext_ver = vext_ver;
> +}
> +
> static void set_feature(CPURISCVState *env, int feature)
> {
> env->features |= (1ULL << feature);
> @@ -320,6 +325,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> CPURISCVState *env = &cpu->env;
> RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> int priv_version = PRIV_VERSION_1_11_0;
> + int vext_version = VEXT_VERSION_0_07_1;
> target_ulong target_misa = 0;
> Error *local_err = NULL;
>
> @@ -345,6 +351,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> }
>
> set_priv_version(env, priv_version);
> + set_vext_version(env, vext_version);
> set_resetvec(env, DEFAULT_RSTVEC);
>
> if (cpu->cfg.mmu) {
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 2e8d01c155..748bd557f9 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -83,6 +83,8 @@ enum {
> #define PRIV_VERSION_1_10_0 0x00011000
> #define PRIV_VERSION_1_11_0 0x00011100
>
> +#define VEXT_VERSION_0_07_1 0x00000701
> +
> #define TRANSLATE_PMP_FAIL 2
> #define TRANSLATE_FAIL 1
> #define TRANSLATE_SUCCESS 0
> @@ -117,6 +119,7 @@ struct CPURISCVState {
> target_ulong badaddr;
>
> target_ulong priv_ver;
> + target_ulong vext_ver;
> target_ulong misa;
> target_ulong misa_mask;
>
> @@ -231,6 +234,8 @@ typedef struct RISCVCPU {
>
> char *priv_spec;
> char *user_spec;
> + uint16_t vlen;
> + uint16_t elen;
> bool mmu;
> bool pmp;
> } cfg;
> --
> 2.23.0
>
