On 2020/2/28 3:36, Richard Henderson wrote:
On 2/25/20 2:35 AM, LIU Zhiwei wrote:+GEN_VEXT_LD_ELEM(vlsb_v_b, int8_t, int8_t, H1, ldsb) +GEN_VEXT_LD_ELEM(vlsb_v_h, int8_t, int16_t, H2, ldsb) +GEN_VEXT_LD_ELEM(vlsb_v_w, int8_t, int32_t, H4, ldsb) +GEN_VEXT_LD_ELEM(vlsb_v_d, int8_t, int64_t, H8, ldsb) +GEN_VEXT_LD_ELEM(vlsh_v_h, int16_t, int16_t, H2, ldsw) +GEN_VEXT_LD_ELEM(vlsh_v_w, int16_t, int32_t, H4, ldsw) +GEN_VEXT_LD_ELEM(vlsh_v_d, int16_t, int64_t, H8, ldsw) +GEN_VEXT_LD_ELEM(vlsw_v_w, int32_t, int32_t, H4, ldl) +GEN_VEXT_LD_ELEM(vlsw_v_d, int32_t, int64_t, H8, ldl) +GEN_VEXT_LD_ELEM(vlse_v_b, int8_t, int8_t, H1, ldsb) +GEN_VEXT_LD_ELEM(vlse_v_h, int16_t, int16_t, H2, ldsw) +GEN_VEXT_LD_ELEM(vlse_v_w, int32_t, int32_t, H4, ldl) +GEN_VEXT_LD_ELEM(vlse_v_d, int64_t, int64_t, H8, ldq) +GEN_VEXT_LD_ELEM(vlsbu_v_b, uint8_t, uint8_t, H1, ldub) +GEN_VEXT_LD_ELEM(vlsbu_v_h, uint8_t, uint16_t, H2, ldub) +GEN_VEXT_LD_ELEM(vlsbu_v_w, uint8_t, uint32_t, H4, ldub) +GEN_VEXT_LD_ELEM(vlsbu_v_d, uint8_t, uint64_t, H8, ldub) +GEN_VEXT_LD_ELEM(vlshu_v_h, uint16_t, uint16_t, H2, lduw) +GEN_VEXT_LD_ELEM(vlshu_v_w, uint16_t, uint32_t, H4, lduw) +GEN_VEXT_LD_ELEM(vlshu_v_d, uint16_t, uint64_t, H8, lduw) +GEN_VEXT_LD_ELEM(vlswu_v_w, uint32_t, uint32_t, H4, ldl) +GEN_VEXT_LD_ELEM(vlswu_v_d, uint32_t, uint64_t, H8, ldl)Why do you need to define new functions identical to the old ones? Are you doing this just to make the names match up?
Yes, just to make the names match up. So I can use GEN_VEXT_ST_STRIDE to generate code. Perhaps add a parameter for GEN_VEXT_ST_STRIDE is just OK.
+GEN_VEXT_ST_ELEM(vssb_v_b, int8_t, H1, stb) +GEN_VEXT_ST_ELEM(vssb_v_h, int16_t, H2, stb) +GEN_VEXT_ST_ELEM(vssb_v_w, int32_t, H4, stb) +GEN_VEXT_ST_ELEM(vssb_v_d, int64_t, H8, stb) +GEN_VEXT_ST_ELEM(vssh_v_h, int16_t, H2, stw) +GEN_VEXT_ST_ELEM(vssh_v_w, int32_t, H4, stw) +GEN_VEXT_ST_ELEM(vssh_v_d, int64_t, H8, stw) +GEN_VEXT_ST_ELEM(vssw_v_w, int32_t, H4, stl) +GEN_VEXT_ST_ELEM(vssw_v_d, int64_t, H8, stl) +GEN_VEXT_ST_ELEM(vsse_v_b, int8_t, H1, stb) +GEN_VEXT_ST_ELEM(vsse_v_h, int16_t, H2, stw) +GEN_VEXT_ST_ELEM(vsse_v_w, int32_t, H4, stl) +GEN_VEXT_ST_ELEM(vsse_v_d, int64_t, H8, stq)Likewise.+static void vext_st_stride(void *vd, void *v0, target_ulong base, + target_ulong stride, CPURISCVState *env, uint32_t desc, + vext_st_elem_fn st_elem, uint32_t esz, uint32_t msz, uintptr_t ra) +{ + uint32_t i, k; + uint32_t nf = vext_nf(desc); + uint32_t vm = vext_vm(desc); + uint32_t mlen = vext_mlen(desc); + uint32_t vlmax = vext_maxsz(desc) / esz; + + /* probe every access*/ + for (i = 0; i < env->vl; i++) { + if (!vm && !vext_elem_mask(v0, mlen, i)) { + continue; + } + probe_write_access(env, base + stride * i, nf * msz, ra); + } + /* store bytes to guest memory */ + for (i = 0; i < env->vl; i++) { + k = 0; + if (!vm && !vext_elem_mask(v0, mlen, i)) { + continue; + } + while (k < nf) { + target_ulong addr = base + stride * i + k * msz; + st_elem(env, addr, i + k * vlmax, vd, ra); + k++; + } + } +}Similar comments wrt unifying the load and store helpers. I'll also note that vext_st_stride and vext_st_us_mask could be unified by passing sizeof(ETYPE) as stride, and vm = true as a parameter.
Good idea. Thanks. Zhiwei
r~
