Re: [PATCH v5 13/60] target/riscv: vector single-width bit shift instructions

[Richard Henderson]

On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +#define GEN_OPIVX_GVEC_SHIFT_TRANS(NAME, GVSUF)                              
>  \
> +static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                       
>  \
> +{                                                                            
>  \
> +    if (!opivx_check(s, a)) {                                                
>  \
> +        return false;                                                        
>  \
> +    }                                                                        
>  \
> +                                                                             
>  \
> +    if (a->vm && s->vl_eq_vlmax) {                                           
>  \
> +        TCGv_i32 src1 = tcg_temp_new_i32();                                  
>  \
> +        TCGv tmp = tcg_temp_new();                                           
>  \
> +        gen_get_gpr(tmp, a->rs1);                                            
>  \
> +        tcg_gen_trunc_tl_i32(src1, tmp);                                     
>  \
> +        tcg_gen_gvec_##GVSUF(8 << s->sew, vreg_ofs(s, a->rd),                
>  \
> +            vreg_ofs(s, a->rs2), src1, MAXSZ(s), MAXSZ(s));                  
>  \

Incorrect first argument.
Prefer an inline funtion helper.

Otherwise,
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>


r~