From: Alistair Francis <alistair.fran...@wdc.com> As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't correctly handling illegal instructions based on the value of MSTATUS_TSR and the current privledge level.
This patch fixes the issue raised in the bug by raising an illegal instruction if TSR is set and we are in S-Mode. Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Reviewed-by: Jonathan Behrens <jonat...@fintelia.io Signed-off-by: Palmer Dabbelt <palmerdabb...@google.com> --- target/riscv/op_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 8736f689c2..c6412f680c 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -85,7 +85,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) } if (env->priv_ver >= PRIV_VERSION_1_10_0 && - get_field(env->mstatus, MSTATUS_TSR)) { + get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } -- 2.25.1.481.gfbce0eb801-goog