On Sun, Apr 12, 2020 at 3:48 PM Philippe Mathieu-Daudé <f4...@amsat.org> wrote: > > Coccinelle reported: > > $ spatch ... --timeout 60 --sp-file \ > scripts/coccinelle/simplify-init-realize-error_propagate.cocci > HANDLING: ./hw/riscv/sifive_u.c > >>> possible moves from riscv_sifive_u_soc_init() to > riscv_sifive_u_soc_realize() in ./hw/riscv/sifive_u.c:473 > > Move the calls using &error_abort which don't depend on input > updated before realize() to init(). > > Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > v3: Typo 'depend of' -> 'depend on' (eblake) > --- > hw/riscv/sifive_u.c | 42 ++++++++++++++++++++++-------------------- > 1 file changed, 22 insertions(+), 20 deletions(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 96177c1977..7bf1f30a35 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -406,6 +406,8 @@ static void riscv_sifive_u_init(MachineState *machine) > static void riscv_sifive_u_soc_init(Object *obj) > { > MachineState *ms = MACHINE(qdev_get_machine()); > + const struct MemmapEntry *memmap = sifive_u_memmap; > + MemoryRegion *system_memory = get_system_memory(); > SiFiveUSoCState *s = RISCV_U_SOC(obj); > > object_initialize_child(obj, "e-cluster", &s->e_cluster, > @@ -443,6 +445,26 @@ static void riscv_sifive_u_soc_init(Object *obj) > TYPE_CADENCE_GEM); > object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision", > &error_abort); > + > + /* boot rom */ > + memory_region_init_rom(&s->mask_rom, obj, "riscv.sifive.u.mrom", > + memmap[SIFIVE_U_MROM].size, &error_fatal); > + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, > + &s->mask_rom); > + > + /* > + * Add L2-LIM at reset size. > + * This should be reduced in size as the L2 Cache Controller WayEnable > + * register is incremented. Unfortunately I don't see a nice (or any) way > + * to handle reducing or blocking out the L2 LIM while still allowing it > + * be re returned to all enabled after a reset. For the time being, just > + * leave it enabled all the time. This won't break anything, but will be > + * too generous to misbehaving guests. > + */ > + memory_region_init_ram(&s->l2lim_mem, NULL, "riscv.sifive.u.l2lim", > + memmap[SIFIVE_U_L2LIM].size, &error_fatal); > + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base, > + &s->l2lim_mem); > } > > static bool sifive_u_get_start_in_flash(Object *obj, Error **errp) > @@ -500,26 +522,6 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, > Error **errp) > object_property_set_bool(OBJECT(&s->u_cluster), true, "realized", > &error_abort); > > - /* boot rom */ > - memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", > - memmap[SIFIVE_U_MROM].size, &error_fatal); > - memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, > - &s->mask_rom); > - > - /* > - * Add L2-LIM at reset size. > - * This should be reduced in size as the L2 Cache Controller WayEnable > - * register is incremented. Unfortunately I don't see a nice (or any) way > - * to handle reducing or blocking out the L2 LIM while still allowing it > - * be re returned to all enabled after a reset. For the time being, just > - * leave it enabled all the time. This won't break anything, but will be > - * too generous to misbehaving guests. > - */ > - memory_region_init_ram(&s->l2lim_mem, NULL, "riscv.sifive.u.l2lim", > - memmap[SIFIVE_U_L2LIM].size, &error_fatal); > - memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base, > - &s->l2lim_mem); > - > /* create PLIC hart topology configuration string */ > plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * > ms->smp.cpus; > -- > 2.21.1 > >