On 4/22/20 8:23 AM, Stephen Long wrote: > Add decoding logic for SVE2 64-bit/32-bit gather non-temporal load > insns. > > 64-bit > * LDNT1SB > * LDNT1B (vector plus scalar) > * LDNT1SH > * LDNT1H (vector plus scalar) > * LDNT1SW > * LDNT1W (vector plus scalar) > * LDNT1D (vector plus scalar) > > 32-bit > * LDNT1SB > * LDNT1B (vector plus scalar) > * LDNT1SH > * LDNT1H (vector plus scalar) > * LDNT1W (vector plus scalar) > > Signed-off-by: Stephen Long <stepl...@quicinc.com> > > I'm not sure I'm initializing xs correctly. This also goes for the > scatter store insns in the previous patch.
You did. xs=0 is 32-bit unsigned offset, xs=1 is 32-bit signed offset (directly from the SVE encoding); I repurpose xs=2 as 64-bit offset. There's a comment in there next to the load/store helper array to that effect. > --- > target/arm/sve.decode | 11 +++++++++++ > target/arm/translate-sve.c | 8 ++++++++ > 2 files changed, 19 insertions(+) Applied to my SVE2 branch. Thanks! r~
