Hi,
I have discovered that MIPS hardware page table walker is not enabled
for any CPU currently available. In this patch I have enable it (and
also CMGCR feature) for P5600 which supports both but they are not
enabled.
This is my first patch to QEMU, I hope it is well formatted and correct.
Signed-off-by: Andrea Oliveri <oliveriand...@gmail.com>
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index 6d145a905a..482cfe2123 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -366,7 +366,7 @@ const mips_def_t mips_defs[] =
},
{
/* FIXME:
- * Config3: CMGCR, PW, VZ, CTXTC, CDMM, TL
+ * Config3: VZ, CTXTC, CDMM, TL
* Config4: MMUExtDef
* Config5: MRP
* FIR(FCR0): Has2008
@@ -380,10 +380,11 @@ const mips_def_t mips_defs[] =
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
(1 << CP0C1_PC) | (1 << CP0C1_FP),
.CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
+ .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
+ (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
(1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) |
- (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 << CP0C3_LPA)
|
- (1 << CP0C3_VInt),
+ (1 << CP0C3_PW) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
+ (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
(0x1c << CP0C4_KScrExist),
.CP0_Config4_rw_bitmask = 0,
