On Wed, Apr 22, 2020 at 05:56:07PM -0700, Vikram Garhwal wrote: > Connect CAN0 and CAN1 to ZCU102 board.
Comments inline. > > Signed-off-by: Vikram Garhwal <fnu.vik...@xilinx.com> > --- > hw/arm/xlnx-zynqmp.c | 26 ++++++++++++++++++++++++++ > include/hw/arm/xlnx-zynqmp.h | 3 +++ > 2 files changed, 29 insertions(+) > > diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c > index b84d153..e5f0d9f 100644 > --- a/hw/arm/xlnx-zynqmp.c > +++ b/hw/arm/xlnx-zynqmp.c > @@ -81,6 +81,14 @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { > 21, 22, > }; > > +static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = { > + 0xFF060000, 0xFF070000, > +}; > + > +static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = { > + 23, 24, > +}; > + > static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { > 0xFF160000, 0xFF170000, > }; > @@ -254,6 +262,11 @@ static void xlnx_zynqmp_init(Object *obj) > TYPE_CADENCE_UART); > } > > + for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { > + sysbus_init_child_obj(obj, "can[*]", &s->can[i], sizeof(s->can[i]), > + TYPE_XLNX_ZYNQMP_CAN); > + } > + > sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata), > TYPE_SYSBUS_AHCI); > > @@ -508,6 +521,19 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error > **errp) > gic_spi[uart_intr[i]]); > } > > + for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { > + object_property_set_int(OBJECT(&s->can[i]), i, "ctrl-idx", > + &error_abort); > + object_property_set_bool(OBJECT(&s->can[i]), true, "realized", &err); > + if (err) { > + error_propagate(errp, err); > + return; > + } > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0, > + gic_spi[can_intr[i]]); > + } > + > object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports", > &error_abort); > object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); > diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h > index 53076fa..2be0ff9 100644 > --- a/include/hw/arm/xlnx-zynqmp.h > +++ b/include/hw/arm/xlnx-zynqmp.h > @@ -22,6 +22,7 @@ > #include "hw/intc/arm_gic.h" > #include "hw/net/cadence_gem.h" > #include "hw/char/cadence_uart.h" > +#include "hw/net/xlnx-zynqmp-can.h" > #include "hw/ide/ahci.h" > #include "hw/sd/sdhci.h" > #include "hw/ssi/xilinx_spips.h" > @@ -41,6 +42,7 @@ > #define XLNX_ZYNQMP_NUM_RPU_CPUS 2 > #define XLNX_ZYNQMP_NUM_GEMS 4 > #define XLNX_ZYNQMP_NUM_UARTS 2 > +#define XLNX_ZYNQMP_NUM_CAN 2 > #define XLNX_ZYNQMP_NUM_SDHCI 2 > #define XLNX_ZYNQMP_NUM_SPIS 2 > #define XLNX_ZYNQMP_NUM_GDMA_CH 8 > @@ -92,6 +94,7 @@ typedef struct XlnxZynqMPState { > > CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; > CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; > + XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN]; All those spaces between type and array look odd here. Without those spaces: Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > SysbusAHCIState sata; > SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; > XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; > -- > 2.7.4 >