On Thu, 30 Apr 2020 11:56:24 +0800 gengdongjiu <gengdong...@huawei.com> wrote:
> On 2020/4/17 21:32, Peter Maydell wrote: > > On Fri, 10 Apr 2020 at 12:46, Dongjiu Geng <gengdong...@huawei.com> wrote: > >> > >> In the ARMv8 platform, the CPU error types includes synchronous external > >> abort(SEA) > >> and SError Interrupt (SEI). If exception happens in guest, host does not > >> know the detailed > >> information of guest, so it is expected that guest can do the recovery. > >> For example, if an > >> exception happens in a guest user-space application, host does not know > >> which application > >> encounters errors, only guest knows it. > >> > >> For the ARMv8 SEA/SEI, KVM or host kernel delivers SIGBUS to notify > >> userspace. > >> After user space gets the notification, it will record the CPER into guest > >> GHES > >> buffer and inject an exception or IRQ to guest. > >> > >> In the current implementation, if the type of SIGBUS is BUS_MCEERR_AR, we > >> will > >> treat it as a synchronous exception, and notify guest with ARMv8 SEA > >> notification type after recording CPER into guest. > > > > Hi. I left a comment on patch 1. The other 3 patches unreviewed > > are 5, 6 and 8, which are all ACPI core code, so that's for > > MST, Igor or Shannon to review. > > Ping MST, Igor and Shannon, sorry for the noise. I put it on my review queue > > > > > Once those have been reviewed, please ping me if you want this > > to go via target-arm.next. > > > > thanks > > -- PMM > > > > . > > >
