On Wed, May 6, 2020 at 5:11 AM Philippe Mathieu-Daudé <phi...@redhat.com> wrote: > > Hi Alistair, > > On 5/6/20 3:12 AM, Alistair Francis wrote: > > The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since > > 4.1. It's not commonly used so let's remove support for it. > > > > Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> > > --- > > target/riscv/cpu.c | 30 ------- > > target/riscv/cpu.h | 8 -- > > target/riscv/csr.c | 82 ++++--------------- > > .../riscv/insn_trans/trans_privileged.inc.c | 6 -- > > tests/qtest/machine-none-test.c | 4 +- > > 5 files changed, 19 insertions(+), 111 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 059d71f2c7..eeb91f8513 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -135,16 +135,6 @@ static void riscv_base32_cpu_init(Object *obj) > > set_misa(env, 0); > > } > > > > -static void rv32gcsu_priv1_09_1_cpu_init(Object *obj) > > -{ > > - CPURISCVState *env = &RISCV_CPU(obj)->env; > > - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > > - set_priv_version(env, PRIV_VERSION_1_09_1); > > - set_resetvec(env, DEFAULT_RSTVEC); > > - set_feature(env, RISCV_FEATURE_MMU); > > - set_feature(env, RISCV_FEATURE_PMP); > > -} > > - > > static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > @@ -182,16 +172,6 @@ static void riscv_base64_cpu_init(Object *obj) > > set_misa(env, 0); > > } > > > > -static void rv64gcsu_priv1_09_1_cpu_init(Object *obj) > > -{ > > - CPURISCVState *env = &RISCV_CPU(obj)->env; > > - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > > - set_priv_version(env, PRIV_VERSION_1_09_1); > > - set_resetvec(env, DEFAULT_RSTVEC); > > - set_feature(env, RISCV_FEATURE_MMU); > > - set_feature(env, RISCV_FEATURE_PMP); > > -} > > - > > static void rv64gcsu_priv1_10_0_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > @@ -388,8 +368,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error > > **errp) > > priv_version = PRIV_VERSION_1_11_0; > > } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { > > priv_version = PRIV_VERSION_1_10_0; > > - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) { > > - priv_version = PRIV_VERSION_1_09_1; > > } else { > > error_setg(errp, > > "Unsupported privilege spec version '%s'", > > @@ -621,18 +599,10 @@ static const TypeInfo riscv_cpu_type_infos[] = { > > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), > > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, > > rv32imafcu_nommu_cpu_init), > > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, > > rv32gcsu_priv1_10_0_cpu_init), > > - /* Depreacted */ > > - DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), > > - DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, > > rv32gcsu_priv1_09_1_cpu_init), > > - DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, > > rv32gcsu_priv1_10_0_cpu_init) > > Shouldn't you let TYPE_RISCV_CPU_RV32GCSU_V1_10_0 until you remove v1.10.0? > > Or remove TYPE_RISCV_CPU_RV32GCSU_V1_10_0 & > TYPE_RISCV_CPU_RV64GCSU_V1_10_0 in another patch after this one > (restricted to 1.09.1).
Fixed in v2, I have split this patch into 2. Alistair > > > #elif defined(TARGET_RISCV64) > > DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init), > > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), > > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, > > rv64gcsu_priv1_10_0_cpu_init), > > - /* Deprecated */ > > - DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), > > - DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, > > rv64gcsu_priv1_09_1_cpu_init), > > - DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, > > rv64gcsu_priv1_10_0_cpu_init) > > Ditto. > > > #endif > > }; > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index d0e7f5b9c5..c022539012 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -40,13 +40,6 @@ > > #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") > > #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") > > #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") > > -/* Deprecated */ > > -#define TYPE_RISCV_CPU_RV32IMACU_NOMMU > > RISCV_CPU_TYPE_NAME("rv32imacu-nommu") > > -#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 > > RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1") > > -#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 > > RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0") > > Ditto. > > > -#define TYPE_RISCV_CPU_RV64IMACU_NOMMU > > RISCV_CPU_TYPE_NAME("rv64imacu-nommu") > > -#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 > > RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1") > > -#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 > > RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0") > > Ditto. > > > > > #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) > > #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) > > @@ -80,7 +73,6 @@ enum { > > RISCV_FEATURE_MISA > > }; > > > > -#define PRIV_VERSION_1_09_1 0x00010901 > > #define PRIV_VERSION_1_10_0 0x00011000 > > #define PRIV_VERSION_1_11_0 0x00011100 > > > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 11d184cd16..df3498b24f 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -58,31 +58,11 @@ static int ctr(CPURISCVState *env, int csrno) > > #if !defined(CONFIG_USER_ONLY) > > CPUState *cs = env_cpu(env); > > RISCVCPU *cpu = RISCV_CPU(cs); > > - uint32_t ctr_en = ~0u; > > > > if (!cpu->cfg.ext_counters) { > > /* The Counters extensions is not enabled */ > > return -1; > > } > > - > > - /* > > - * The counters are always enabled at run time on newer priv specs, as > > the > > - * CSR has changed from controlling that the counters can be read to > > - * controlling that the counters increment. > > - */ > > - if (env->priv_ver > PRIV_VERSION_1_09_1) { > > - return 0; > > - } > > - > > - if (env->priv < PRV_M) { > > - ctr_en &= env->mcounteren; > > - } > > - if (env->priv < PRV_S) { > > - ctr_en &= env->scounteren; > > - } > > - if (!(ctr_en & (1u << (csrno & 31)))) { > > - return -1; > > - } > > #endif > > return 0; > > } > > @@ -358,34 +338,21 @@ static int write_mstatus(CPURISCVState *env, int > > csrno, target_ulong val) > > int dirty; > > > > /* flush tlb on mstatus fields that affect VM */ > > - if (env->priv_ver <= PRIV_VERSION_1_09_1) { > > - if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | > > - MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { > > - tlb_flush(env_cpu(env)); > > - } > > - mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | > > - MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | > > - MSTATUS_MPP | MSTATUS_MXR | > > - (validate_vm(env, get_field(val, MSTATUS_VM)) ? > > - MSTATUS_VM : 0); > > + if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | > > + MSTATUS_MPRV | MSTATUS_SUM)) { > > + tlb_flush(env_cpu(env)); > > } > > - if (env->priv_ver >= PRIV_VERSION_1_10_0) { > > - if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | > > - MSTATUS_MPRV | MSTATUS_SUM)) { > > - tlb_flush(env_cpu(env)); > > - } > > - mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | > > - MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | > > - MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | > > - MSTATUS_TW; > > + mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | > > + MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | > > + MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | > > + MSTATUS_TW; > > #if defined(TARGET_RISCV64) > > - /* > > - * RV32: MPV and MTL are not in mstatus. The current plan is to > > - * add them to mstatush. For now, we just don't support it. > > - */ > > - mask |= MSTATUS_MTL | MSTATUS_MPV; > > + /* > > + * RV32: MPV and MTL are not in mstatus. The current plan is to > > + * add them to mstatush. For now, we just don't support it. > > + */ > > + mask |= MSTATUS_MTL | MSTATUS_MPV; > > #endif > > - } > > > > mstatus = (mstatus & ~mask) | (val & mask); > > > > @@ -553,8 +520,7 @@ static int write_mcounteren(CPURISCVState *env, int > > csrno, target_ulong val) > > /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ > > static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong > > *val) > > { > > - if (env->priv_ver > PRIV_VERSION_1_09_1 > > - && env->priv_ver < PRIV_VERSION_1_11_0) { > > + if (env->priv_ver < PRIV_VERSION_1_11_0) { > > return -1; > > } > > *val = env->mcounteren; > > @@ -564,8 +530,7 @@ static int read_mscounteren(CPURISCVState *env, int > > csrno, target_ulong *val) > > /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ > > static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong > > val) > > { > > - if (env->priv_ver > PRIV_VERSION_1_09_1 > > - && env->priv_ver < PRIV_VERSION_1_11_0) { > > + if (env->priv_ver < PRIV_VERSION_1_11_0) { > > return -1; > > } > > env->mcounteren = val; > > @@ -574,20 +539,13 @@ static int write_mscounteren(CPURISCVState *env, int > > csrno, target_ulong val) > > > > static int read_mucounteren(CPURISCVState *env, int csrno, target_ulong > > *val) > > { > > - if (env->priv_ver > PRIV_VERSION_1_09_1) { > > - return -1; > > - } > > - *val = env->scounteren; > > + return -1; > > return 0; > > } > > > > static int write_mucounteren(CPURISCVState *env, int csrno, target_ulong > > val) > > { > > - if (env->priv_ver > PRIV_VERSION_1_09_1) { > > - return -1; > > - } > > - env->scounteren = val; > > - return 0; > > + return -1; > > } > > > > /* Machine Trap Handling */ > > @@ -829,13 +787,7 @@ static int write_satp(CPURISCVState *env, int csrno, > > target_ulong val) > > if (!riscv_feature(env, RISCV_FEATURE_MMU)) { > > return 0; > > } > > - if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) { > > - tlb_flush(env_cpu(env)); > > - env->sptbr = val & (((target_ulong) > > - 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1); > > - } > > - if (env->priv_ver >= PRIV_VERSION_1_10_0 && > > - validate_vm(env, get_field(val, SATP_MODE)) && > > + if (validate_vm(env, get_field(val, SATP_MODE)) && > > ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) > > { > > if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { > > diff --git a/target/riscv/insn_trans/trans_privileged.inc.c > > b/target/riscv/insn_trans/trans_privileged.inc.c > > index 76c2fad71c..1af9fa7df8 100644 > > --- a/target/riscv/insn_trans/trans_privileged.inc.c > > +++ b/target/riscv/insn_trans/trans_privileged.inc.c > > @@ -95,12 +95,6 @@ static bool trans_sfence_vma(DisasContext *ctx, > > arg_sfence_vma *a) > > > > static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a) > > { > > -#ifndef CONFIG_USER_ONLY > > - if (ctx->priv_ver <= PRIV_VERSION_1_09_1) { > > - gen_helper_tlb_flush(cpu_env); > > - return true; > > - } > > -#endif > > return false; > > } > > > > diff --git a/tests/qtest/machine-none-test.c > > b/tests/qtest/machine-none-test.c > > index 8bb54a6360..b52311ec2e 100644 > > --- a/tests/qtest/machine-none-test.c > > +++ b/tests/qtest/machine-none-test.c > > @@ -54,8 +54,8 @@ static struct arch2cpu cpus_map[] = { > > { "xtensa", "dc233c" }, > > { "xtensaeb", "fsf" }, > > { "hppa", "hppa" }, > > - { "riscv64", "rv64gcsu-v1.10.0" }, > > - { "riscv32", "rv32gcsu-v1.9.1" }, > > + { "riscv64", "sifive-u54" }, > > + { "riscv32", "sifive-u34" }, > > { "rx", "rx62n" }, > > }; > > > > >