By default the virtio-iommu translates MSI transactions. This behavior is inherited from ARM SMMU. However the virt machine code knows where the MSI doorbells are, so we can easily declare those regions as VIRTIO_IOMMU_RESV_MEM_T_MSI. With that setting the guest iommu subsystem will not need to map MSIs. This setup will simplify the VFIO integration.
In this series, the ITS or GICV2M doorbells are declared as HW MSI regions to be bypassed by the VIRTIO-IOMMU. This also paves the way to the x86 integration where the MSI region, [0xFEE00000,0xFEEFFFFF], will be exposed by the q35 machine. However this will be handled in a separate series when not-DT support gets resolved. Best Regards Eric This series can be found at: https://github.com/eauger/qemu/tree/v5.0.0-virtio-iommu-msi-bypass-v2 History: v1 -> v2: - check which MSI controller is in use and advertise the corresponding MSI doorbell - managed for both ITS and GICv2M - various fixes spotted by Peter and Jean-Philippe, see individual logs v1: Most of those patches were respinned from [PATCH for-5.0 v11 00/20] VIRTIO-IOMMU device except the last one which is new Eric Auger (5): qdev: Introduce DEFINE_PROP_RESERVED_REGION virtio-iommu: Implement RESV_MEM probe request virtio-iommu: Handle reserved regions in the translation process virtio-iommu-pci: Add array of Interval properties hw/arm/virt: Let the virtio-iommu bypass MSIs include/exec/memory.h | 6 ++ include/hw/arm/virt.h | 6 ++ include/hw/qdev-properties.h | 3 + include/hw/virtio/virtio-iommu.h | 2 + include/qemu/typedefs.h | 1 + hw/arm/virt.c | 18 +++++ hw/core/qdev-properties.c | 89 ++++++++++++++++++++++++ hw/virtio/virtio-iommu-pci.c | 3 + hw/virtio/virtio-iommu.c | 114 +++++++++++++++++++++++++++++-- hw/virtio/trace-events | 1 + 10 files changed, 239 insertions(+), 4 deletions(-) -- 2.20.1