Hello, This series completes the PowerNV POWER10 machine with the XIVE2 interrupt controller and the PHB5 PCI host bridge controller.
The XIVE2 interrupt controller of the POWER10 processor follows the same logic than on POWER9 but the HW interface has been largely reviewed. To avoid adding too much complexity in the P9 XIVE models, a new XIVE2 core framework is introduced. The PHB5 and PHB4 controllers are very similar. Not much changes there apart from the mapping addresses and ids. There is more to come on PHB5 regarding interrupt offload on the interrupt controller, but this is for another round. This series also adds basic OCC and CPU Quad models which are not very much exercised by the firmware. Thanks, C. Cédric Le Goater (9): ppc/xive: Export PQ get/set routines ppc/xive: Export xive_presenter_notify() ppc/xive2: Introduce a XIVE2 core framework ppc/xive2: Introduce a presenter matching routine ppc/pnv: Add a XIVE2 controller to the POWER10 chip. ppc/pnv: Add a OCC model for POWER10 ppc/pnv: Add POWER10 quads ppc/pnv: Add model for POWER9 PHB5 PCIe Host bridge ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10) hw/intc/pnv_xive2_regs.h | 428 +++++++ include/hw/pci-host/pnv_phb4.h | 11 + include/hw/ppc/pnv.h | 30 + include/hw/ppc/pnv_occ.h | 2 + include/hw/ppc/pnv_xive.h | 71 ++ include/hw/ppc/pnv_xscom.h | 12 + include/hw/ppc/xive.h | 8 + include/hw/ppc/xive2.h | 93 ++ include/hw/ppc/xive2_regs.h | 198 ++++ hw/intc/pnv_xive2.c | 2026 ++++++++++++++++++++++++++++++++ hw/intc/spapr_xive_kvm.c | 8 +- hw/intc/xive.c | 14 +- hw/intc/xive2.c | 756 ++++++++++++ hw/pci-host/pnv_phb4_pec.c | 44 + hw/ppc/pnv.c | 243 +++- hw/ppc/pnv_occ.c | 17 + hw/ppc/pnv_psi.c | 32 +- hw/intc/Makefile.objs | 4 +- 18 files changed, 3974 insertions(+), 23 deletions(-) create mode 100644 hw/intc/pnv_xive2_regs.h create mode 100644 include/hw/ppc/xive2.h create mode 100644 include/hw/ppc/xive2_regs.h create mode 100644 hw/intc/pnv_xive2.c create mode 100644 hw/intc/xive2.c -- 2.25.4