On Thu, May 21, 2020 at 7:48 AM Philippe Mathieu-Daudé <f4...@amsat.org> wrote: > > On 5/21/20 4:42 PM, Bin Meng wrote: > > From: Bin Meng <bin.m...@windriver.com> > > > > To keep consistency with the machine* functions, remove the riscv_ > > prefix of the soc* functions. > > > > Signed-off-by: Bin Meng <bin.m...@windriver.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > > --- > > > > hw/riscv/sifive_u.c | 24 ++++++++++++------------ > > 1 file changed, 12 insertions(+), 12 deletions(-) > > > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > > index 4299bdf..f9fef2b 100644 > > --- a/hw/riscv/sifive_u.c > > +++ b/hw/riscv/sifive_u.c > > @@ -481,7 +481,7 @@ static void sifive_u_machine_init_register_types(void) > > > > type_init(sifive_u_machine_init_register_types) > > > > -static void riscv_sifive_u_soc_init(Object *obj) > > +static void sifive_u_soc_instance_init(Object *obj) > > { > > MachineState *ms = MACHINE(qdev_get_machine()); > > SiFiveUSoCState *s = RISCV_U_SOC(obj); > > @@ -520,7 +520,7 @@ static void riscv_sifive_u_soc_init(Object *obj) > > TYPE_CADENCE_GEM); > > } > > > > -static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) > > +static void sifive_u_soc_realize(DeviceState *dev, Error **errp) > > { > > MachineState *ms = MACHINE(qdev_get_machine()); > > SiFiveUSoCState *s = RISCV_U_SOC(dev); > > @@ -635,32 +635,32 @@ static void riscv_sifive_u_soc_realize(DeviceState > > *dev, Error **errp) > > memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); > > } > > > > -static Property riscv_sifive_u_soc_props[] = { > > +static Property sifive_u_soc_props[] = { > > DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), > > DEFINE_PROP_END_OF_LIST() > > }; > > > > -static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) > > +static void sifive_u_soc_class_init(ObjectClass *oc, void *data) > > { > > DeviceClass *dc = DEVICE_CLASS(oc); > > > > - device_class_set_props(dc, riscv_sifive_u_soc_props); > > - dc->realize = riscv_sifive_u_soc_realize; > > + device_class_set_props(dc, sifive_u_soc_props); > > + dc->realize = sifive_u_soc_realize; > > /* Reason: Uses serial_hds in realize function, thus can't be used > > twice */ > > dc->user_creatable = false; > > } > > > > -static const TypeInfo riscv_sifive_u_soc_type_info = { > > +static const TypeInfo sifive_u_soc_type_info = { > > .name = TYPE_RISCV_U_SOC, > > .parent = TYPE_DEVICE, > > .instance_size = sizeof(SiFiveUSoCState), > > - .instance_init = riscv_sifive_u_soc_init, > > - .class_init = riscv_sifive_u_soc_class_init, > > + .instance_init = sifive_u_soc_instance_init, > > + .class_init = sifive_u_soc_class_init, > > }; > > > > -static void riscv_sifive_u_soc_register_types(void) > > +static void sifive_u_soc_register_types(void) > > { > > - type_register_static(&riscv_sifive_u_soc_type_info); > > + type_register_static(&sifive_u_soc_type_info); > > } > > > > -type_init(riscv_sifive_u_soc_register_types) > > +type_init(sifive_u_soc_register_types) > > > > Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> > >