On 5/20/20 11:24 PM, Paul Zimmerman wrote:
> On Wed, May 20, 2020 at 6:18 AM Peter Maydell <peter.mayd...@linaro.org
> <mailto:peter.mayd...@linaro.org>> wrote:
>
> On Wed, 20 May 2020 at 06:49, Paul Zimmerman <pauld...@gmail.com
> <mailto:pauld...@gmail.com>> wrote:
> > Is there a tree somewhere that has a working example of a
> > three-phase reset? I did a 'git grep' on the master branch and didn't
> > find any code that is actually using it. I tried to implement it from
> > the example in reset.rst, but I'm getting a segfault on the first
> line in
> > resettable_class_set_parent_phases() that I'm having trouble figuring
> > out.
>
> Hmm, I thought we'd committed a change of a device to use the new
> mechanism along with the actual implementation but I can't see it
> now. Damien, what's the status with getting Xilinx devices to use the
> 3-phase reset API?
>
>
> Never mind, I found the problem, I wasn't initializing my class properly.
> It's working now,I'll send along a new patch series shortly.
>
> Thanks,
> Paul
>
Sorry, I was off grid during the last days.
It's a bit late but if anyone is looking of examples theses xilinx
devices are in the tree:
+ hw/char/cadence_uart.c
+ hw/misc/zynq_slcr.c
Damien
