On Tue, May 26, 2020 at 6:58 PM LIU Zhiwei <zhiwei_...@c-sky.com> wrote: > > > > On 2020/5/27 1:12, Alistair Francis wrote: > > On Fri, May 22, 2020 at 12:51 AM LIU Zhiwei <zhiwei_...@c-sky.com> wrote: > >> > >> > >> On 2020/5/20 5:31, Alistair Francis wrote: > >>> Ibex is a small and efficient, 32-bit, in-order RISC-V core with > >>> a 2-stage pipeline that implements the RV32IMC instruction set > >>> architecture. > >>> > >>> For more details on lowRISC see here: > >>> https://github.com/lowRISC/ibex > >>> > >>> Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> > >>> Reviewed-by: Bin Meng <bin.m...@windriver.com> > >>> --- > >>> target/riscv/cpu.h | 1 + > >>> target/riscv/cpu.c | 10 ++++++++++ > >>> 2 files changed, 11 insertions(+) > >>> > >>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > >>> index d0e7f5b9c5..8733d7467f 100644 > >>> --- a/target/riscv/cpu.h > >>> +++ b/target/riscv/cpu.h > >>> @@ -35,6 +35,7 @@ > >>> #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") > >>> #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") > >>> #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") > >>> +#define TYPE_RISCV_CPU_IBEX > >>> RISCV_CPU_TYPE_NAME("lowrisc-ibex") > >>> #define TYPE_RISCV_CPU_SIFIVE_E31 > >>> RISCV_CPU_TYPE_NAME("sifive-e31") > >>> #define TYPE_RISCV_CPU_SIFIVE_E34 > >>> RISCV_CPU_TYPE_NAME("sifive-e34") > >>> #define TYPE_RISCV_CPU_SIFIVE_E51 > >>> RISCV_CPU_TYPE_NAME("sifive-e51") > >>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > >>> index 5eb3c02735..eb2bbc87ae 100644 > >>> --- a/target/riscv/cpu.c > >>> +++ b/target/riscv/cpu.c > >>> @@ -156,6 +156,15 @@ static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) > >>> set_feature(env, RISCV_FEATURE_PMP); > >>> } > >>> > >>> +static void rv32imcu_nommu_cpu_init(Object *obj) > >>> +{ > >>> + CPURISCVState *env = &RISCV_CPU(obj)->env; > >>> + set_misa(env, RV32 | RVI | RVM | RVC | RVU); > >>> + set_priv_version(env, PRIV_VERSION_1_10_0); > >>> + set_resetvec(env, 0x8090); > >> Hi Alistair, > >> > >> I see all RISC-V cpus have an reset vector which acts as the first pc > >> when machine boots up. > >> However, the first pc is more like an attribute of a machine, not a cpu. > > In general it seems to be a CPU property. I assume that some CPUs > > would allow the reset vector to be selectable though, in which case it > > becomes a board property. > > > >> Another reason is that the cpu names are a combination of ISA. > >> Then the cpus from different vendors may have same ISA, with different > >> reset vectors. > >> > >> Do you think so? > > If you are worried about CPUs with different vectors we could always > > make it a property in the future and have boards override it. I don't > > think we need that yet (only 1 CPU is different) but it is an easy > > future change. > I think your are right. A cpu reset vector property is better. If there > is a conflict in the future, > we can add the property there. > > Reviewed-by: LIU Zhiwei <zhiwei_...@c-sky.com>
Great! Thanks :) Alistair > > Zhiwei