11:06 Pet, 05.06.2020. Jiaxun Yang <jiaxun.y...@flygoat.com> је написао/ла: > > On Fri, 5 Jun 2020 10:38:36 +0200 > Aleksandar Markovic <aleksandar.qemu.de...@gmail.com> wrote: > > > уто, 2. јун 2020. у 04:38 Huacai Chen <zltjiang...@gmail.com> је > > написао/ла: > > > > > > Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and > > > Loongson-3B R1/R2. > > > > Hi, Huacai, > > > > The documents you kindly provided contain some valuable info on > > Loongson-3A R1/R2/R3/R4 and Loongson-3B R1/R2. However, I > > couldn't find detailed instruction-by-instruction specifications. > > > > In fact, I don't need all the details right now, but some form of > > overview of instructions sets of Loongson-3A R1/R2/R3/R4 and > > Loongson-3B R1/R2. Could you please provide textual description > > (one of two paragraph) of supported instructions for each of these > > models: > > > > Hi Aleksandar, > > I'm going to explain this according to the names of vendor specified > ASEs name in GCC & Binutils. > > There are some instruction that not covered by public documents, that's > out of our scope so I'm not going to talk them. > > Firstly, there are some ASEs not being upstreamed yet: > - Loongson-AMO (Atomic Opreations, Looks like RISC-V) > - Loongson-EXT3 (Loongson Extention 3) > - Loongson-CSR (Core Status Registers, instructions to read some > private core register, including something called "stable-counter" > (TSC like timer) and CPUCFG(something like cpuid in x86)) > > - MIPS-MSA-Ctypto (Including AES, SHA, MD5 stuff) > - MIPS MSA2 (256-bit MSA instructions) > > And there is a ASE that only being used in kernel so not even being > mentioned in toolchain. > - Loongson-SPW (LWPTE, LDPTE used to help with pagetable walking) > > ALl these processors have mips64r2 as baseline. > > > * Loongson-3A R1 > Loongson-MMI, Loongson-EXT > > > * Loongson-3A R2 > Loongson-MMI, Loongson-EXT, Looongson-EXT2, Loongson-SPW, DSP, DSPr2 > > > * Loongson-3A R3 > Same as R2. This revision mainly focus on bugfix and improve clock > speed. > > > * Loongson-3A R4 > Loongson-MMI, Loongson-EXT, Looongson-EXT2, Loongson-SPW, Loongson-AMO, > Loongson-EXT3, Loongson-CSR, MSA Crypto, MSA2 > > This processor even support hardware unaligned accessing. > > > * Loongson-3B R1 > > * Loongson-3B R2 > Loongson-3B R1 and R2 are mostly identical with Loongson-3A R1, the > difference is it have 8-cores in a package. It was designed for HPC so > there are some domain specific SIMD instructions, but they're not > available to public. > > And a new family member of Loongson64: > Loongson-2K (R1): > Loongson-MMI, Loongson-EXT, Looongson-EXT2, MSA. >
Thanks for your detailed response, Juaxun. I will think over the weekend about the new aspects you mentioned here. All this is valuable info for long-term planning. But also in short-term - for this very series. Expect my answer early next week. Best Regards and Best Health! Aleksandar > > > > (what is the base instructuin set; the difference to the previous > > model; what SIMD extension (LMI/MSA) is supported other specifics > > around supported instructions) > > > > Based on your answer I may bring forward some suggestions on the > > improvement of v4 of this series. > > > > Truly yours, > > Aleksandar > > > > Thank a lot. > > - Jiaxun