On Fri, Jun 5, 2020 at 12:40 AM Bin Meng <bmeng...@gmail.com> wrote:
>
> From: Bin Meng <bin.m...@windriver.com>
>
> There is no need to have two functions that have exactly the same
> codes for 32-bit and 64-bit base CPUs.
>
> Signed-off-by: Bin Meng <bin.m...@windriver.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
>
> target/riscv/cpu.c | 18 +++++-------------
> 1 file changed, 5 insertions(+), 13 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9007a25..d38d829 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -126,9 +126,7 @@ static void riscv_any_cpu_init(Object *obj)
> set_resetvec(env, DEFAULT_RSTVEC);
> }
>
> -#if defined(TARGET_RISCV32)
> -
> -static void riscv_base32_cpu_init(Object *obj)
> +static void riscv_base_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> /* We set this in the realise function */
> @@ -136,6 +134,8 @@ static void riscv_base32_cpu_init(Object *obj)
> set_resetvec(env, DEFAULT_RSTVEC);
> }
>
> +#if defined(TARGET_RISCV32)
> +
> static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -173,14 +173,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj)
>
> #elif defined(TARGET_RISCV64)
>
> -static void riscv_base64_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - /* We set this in the realise function */
> - set_misa(env, 0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> -}
> -
> static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -601,13 +593,13 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> },
> DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
> #if defined(TARGET_RISCV32)
> - DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,
> rv32gcsu_priv1_10_0_cpu_init),
> #elif defined(TARGET_RISCV64)
> - DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,
> rv64gcsu_priv1_10_0_cpu_init),
> #endif
> --
> 2.7.4
>
>
