Hi Alistair, On Thu, Jun 18, 2020 at 12:40 AM Alistair Francis <alistai...@gmail.com> wrote: > > On Mon, Jun 15, 2020 at 5:51 PM Bin Meng <bmeng...@gmail.com> wrote: > > > > From: Bin Meng <bin.m...@windriver.com> > > > > Per the SiFive manual, all E/U series CPU cores' reset vector is > > at 0x1004. Update our codes to match the hardware. > > > > Signed-off-by: Bin Meng <bin.m...@windriver.com> > > This commit breaks my Oreboot test. > > Oreboot starts in flash and we run the command with the > `sifive_u,start-in-flash=true` machine.
Could you please post an Oreboot binary for testing somewhere, or some instructions so that I can test this? > > I have removed this and the later patches from the RISC-V branch. I > want to send a PR today. After that I'll look into this. Regards, Bin
