On Wed, Jun 17, 2020 at 3:30 AM Atish Patra <atish.pa...@wdc.com> wrote: > > Currently, all riscv machines have identical reset vector code > implementations with memory addresses being different for all machines. > They can be easily combined into a single function in common code. > > Move it to common function and let all the machines use the common function. > > Signed-off-by: Atish Patra <atish.pa...@wdc.com> > --- > hw/riscv/boot.c | 46 +++++++++++++++++++++++++++++++++++++++++ > hw/riscv/sifive_u.c | 38 +++-------------------------------
sifive_u's reset vector has to be different to emulate the real hardware MSEL pin state. Please rebase this on top of the following series: http://patchwork.ozlabs.org/project/qemu-devel/list/?series=183567 > hw/riscv/spike.c | 38 +++------------------------------- > hw/riscv/virt.c | 37 +++------------------------------ > include/hw/riscv/boot.h | 2 ++ > 5 files changed, 57 insertions(+), 104 deletions(-) > Regards, Bin
