On Wed, 10 Jun 2020 15:13:49 PDT (-0700), alistai...@gmail.com wrote:
> On Thu, May 28, 2020 at 11:13 AM Alistair Francis <alistai...@gmail.com>
wrote:
>>
>> On Thu, May 21, 2020 at 8:57 AM Alistair Francis <alistai...@gmail.com>
wrote:
>> >
>> > On Wed, May 20, 2020 at 4:08 PM Palmer Dabbelt <pal...@dabbelt.com> wrote:
>> > >
>> > > On Thu, 14 May 2020 13:47:10 PDT (-0700), Alistair Francis wrote:
>> > > > Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
>> > > > ---
>> > > > hw/riscv/sifive_e.c | 35 +++++++++++++++++++++++++++++++----
>> > > > include/hw/riscv/sifive_e.h | 1 +
>> > > > 2 files changed, 32 insertions(+), 4 deletions(-)
>> > > >
>> > > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
>> > > > index 472a98970b..cb7818341b 100644
>> > > > --- a/hw/riscv/sifive_e.c
>> > > > +++ b/hw/riscv/sifive_e.c
>> > > > @@ -98,10 +98,14 @@ static void riscv_sifive_e_init(MachineState
*machine)
>> > > > memmap[SIFIVE_E_DTIM].base, main_mem);
>> > > >
>> > > > /* Mask ROM reset vector */
>> > > > - uint32_t reset_vec[2] = {
>> > > > - 0x204002b7, /* 0x1000: lui t0,0x20400 */
>> > > > - 0x00028067, /* 0x1004: jr t0 */
>> > > > - };
>> > > > + uint32_t reset_vec[2];
>> > > > +
>> > > > + if (s->revb) {
>> > > > + reset_vec[0] = 0x200102b7; /* 0x1000: lui
t0,0x20010 */
>> > > > + } else {
>> > > > + reset_vec[0] = 0x204002b7; /* 0x1000: lui
t0,0x20400 */
>> > > > + }
>> > > > + reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
>> > > >
>> > > > /* copy in the reset vector in little_endian byte order */
>> > > > for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
>> > > > @@ -115,8 +119,31 @@ static void riscv_sifive_e_init(MachineState
*machine)
>> > > > }
>> > > > }
>> > > >
>> > > > +static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
>> > > > +{
>> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
>> > > > +
>> > > > + return s->revb;
>> > > > +}
>> > > > +
>> > > > +static void sifive_e_machine_set_revb(Object *obj, bool value, Error
**errp)
>> > > > +{
>> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
>> > > > +
>> > > > + s->revb = value;
>> > > > +}
>> > > > +
>> > > > static void sifive_e_machine_instance_init(Object *obj)
>> > > > {
>> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
>> > > > +
>> > > > + s->revb = false;
>> > > > + object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
>> > > > + sifive_e_machine_set_revb, NULL);
>> > > > + object_property_set_description(obj, "revb",
>> > > > + "Set on to tell QEMU that it should
model "
>> > > > + "the revB HiFive1 board",
>> > > > + NULL);
>> > > > }
>> > > >
>> > > > static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
>> > > > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
>> > > > index 414992119e..0d3cd07fcc 100644
>> > > > --- a/include/hw/riscv/sifive_e.h
>> > > > +++ b/include/hw/riscv/sifive_e.h
>> > > > @@ -45,6 +45,7 @@ typedef struct SiFiveEState {
>> > > >
>> > > > /*< public >*/
>> > > > SiFiveESoCState soc;
>> > > > + bool revb;
>> > > > } SiFiveEState;
>> > > >
>> > > > #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
>> > >
>> > > IIRC there are way more differences between the un-suffixed FE310 and
the Rev
>> > > B, specifically the interrupt map is all different.
>> >
>> > The three IRQs that QEMU uses for the SiFive E (UART0, UART1 and GPIO)
>> > all seem to be the same.
>>
>> Ping!
>
> Ping^2
>
> Applying to RISC-V tree.
They're not: uart0 is interrupt 3 on the rev b but 5 on the non-rev b (which
they don't call rev a but I'm going to :)). There's isn't even a uart1 in the
DTS on the rev a, and the GPIO interrupts are different as well.
The DTS files are in SiFive's SDK:
https://github.com/sifive/freedom-e-sdk/blob/master/bsp/sifive-hifive1-revb/core.dts
https://github.com/sifive/freedom-e-sdk/blob/master/bsp/sifive-hifive1/core.dts
which should also generate some test programs. When I was there we tested on
QEMU for the platforms that were supported, so there should be some support for
doing so still.
