We use the IDE register with IPIs as a mask to keep track which processors
have already acknowledged the respective interrupt. So we need to initialize
it to 0 to make sure that it doesn't accidently fire an IPI on CPU0 when the
first IPI is triggered.
Reported-by: Elie Richa <ri...@adacore.com>
Signed-off-by: Alexander Graf <ag...@suse.de>
---
hw/openpic.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 9ac3b3d..1f7753d 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -1304,6 +1304,10 @@ static void mpic_reset (void *opaque)
mpp->src[i].ipvp = 0x80800000;
mpp->src[i].ide = 0x00000001;
}
+ /* Set IDE for IPIs to 0 so we don't get spurious interrupts */
+ for (i = mpp->irq_ipi0; i < MAX_IPI; i++) {
+ mpp->src[i].ide = 0;
+ }
/* Initialise IRQ destinations */
for (i = 0; i < MAX_CPU; i++) {
mpp->dst[i].pctp = 0x0000000F;
--
1.6.0.2
