> On Jun 25, 2020, at 12:42 PM, Richard Henderson
> <richard.hender...@linaro.org> wrote:
>
> On 6/25/20 10:00 AM, Lijun Pan wrote:
>> +static void gen_brh(DisasContext *ctx)
>> +{
>> + TCGv_i64 t0 = tcg_temp_new_i64();
>> + TCGv_i64 t1 = tcg_temp_new_i64();
>> + TCGv_i64 t2 = tcg_temp_new_i64();
>> +
>> + tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull);
>> + tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8);
>> + tcg_gen_and_i64(t2, t1, t0);
>> + tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0);
>> + tcg_gen_shli_i64(t1, t1, 8);
>> + tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2);
>> +
>> + tcg_temp_free_i64(t0);
>> + tcg_temp_free_i64(t1);
>> + tcg_temp_free_i64(t2);
>> +}
>> +
>> static opcode_t opcodes[] = {
>> +#if defined(TARGET_PPC64)
>> +GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310),
>> +GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310),
>> +GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310),
>> +#endif
>
> No. You haven't even tested this -- it doesn't compile.
>
>> CC ppc-softmmu/target/ppc/translate.o
>> /home/rth/qemu/qemu/target/ppc/translate.c: In function ‘gen_brd’:
>> /home/rth/qemu/qemu/target/ppc/translate.c:6980:32: error: passing argument
>> 1 of ‘tcg_gen_bswap64_i64’ from incompatible pointer type
>> [-Werror=incompatible-pointer-types]
>> 6980 | tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)],
>> cpu_gpr[rS(ctx->opcode)]);
>> | ~~~~~~~^~~~~~~~~~~~~~~~~
>> | |
>> | TCGv_i32 {aka struct TCGv_i32_d *}
>> In file included from /home/rth/qemu/qemu/target/ppc/translate.c:26:
>> /home/rth/qemu/qemu/include/tcg/tcg-op.h:533:35: note: expected ‘TCGv_i64’
>> {aka ‘struct TCGv_i64_d *’} but argument is of type ‘TCGv_i32’ {aka ‘struct
>> TCGv_i32_d *’}
>> 533 | void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg);
>> | ~~~~~~~~~^~~
>> /home/rth/qemu/qemu/target/ppc/translate.c:6980:58: error: passing argument
>> 2 of ‘tcg_gen_bswap64_i64’ from incompatible pointer type
>> [-Werror=incompatible-pointer-types]
>> 6980 | tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)],
>> cpu_gpr[rS(ctx->opcode)]);
>> |
>> ~~~~~~~^~~~~~~~~~~~~~~~~
>> | |
>> | TCGv_i32
>> {aka struct TCGv_i32_d *}
>
> and so forth.
>
> I warned you before about this. Why are you still building only a restricted
> set of targets?
>
I will configure all the target-list, and add "#if defined(TARGET_PPC64)" for
all gen_brd/w/h().
Lijun