On 7/10/20 3:48 AM, frank.ch...@sifive.com wrote:
> From: LIU Zhiwei <zhiwei_...@c-sky.com>
>
> Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
> Signed-off-by: Frank Chang <frank.ch...@sifive.com>
> ---
> target/riscv/cpu.h | 2 ++
> target/riscv/translate.c | 1 +
> 2 files changed, 3 insertions(+)
This belongs with the second half of the previous patch, the translate portion.
r~
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0cf3fe9456..c02690ed0d 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -361,6 +361,7 @@ void riscv_cpu_set_fflags(CPURISCVState *env,
> target_ulong);
>
> #define TB_FLAGS_MMU_MASK 3
> #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
> +#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
>
> typedef CPURISCVState CPUArchState;
> typedef RISCVCPU ArchCPU;
> @@ -411,6 +412,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState
> *env, target_ulong *pc,
>
> #ifdef CONFIG_USER_ONLY
> flags |= TB_FLAGS_MSTATUS_FS;
> + flags |= TB_FLAGS_MSTATUS_VS;
> #else
> flags |= cpu_mmu_index(env, 0);
> if (riscv_cpu_fp_enabled(env)) {
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index a806e33301..02b4204584 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -796,6 +796,7 @@ static void riscv_tr_init_disas_context(DisasContextBase
> *dcbase, CPUState *cs)
> ctx->pc_succ_insn = ctx->base.pc_first;
> ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK;
> ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
> + ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS;
> ctx->priv_ver = env->priv_ver;
> #if !defined(CONFIG_USER_ONLY)
> if (riscv_has_ext(env, RVH)) {
>
