From: Frank Chang <frank.ch...@sifive.com> Add the following instructions:
* vl1r.v * vs1r.v Signed-off-by: Frank Chang <frank.ch...@sifive.com> --- target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 4 ++ target/riscv/insn_trans/trans_rvv.inc.c | 61 +++++++++++++++++++++++++ target/riscv/vector_helper.c | 47 +++++++++++++++++++ 4 files changed, 115 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 808f88fbeb..8cf5c4c065 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -145,6 +145,9 @@ DEF_HELPER_5(vle16ff_v, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vle32ff_v, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vle64ff_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_4(vl1r_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vs1r_v, void, ptr, tl, env, i32) + DEF_HELPER_6(vamoswapei8_32_v, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamoswapei8_64_v, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamoswapei16_32_v, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 6a9cf6ad53..e3f0fba912 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -267,6 +267,10 @@ vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm +# Vector whole register insns +vl1r_v 000 000 1 01000 ..... 000 ..... 0000111 @r2 +vs1r_v 000 000 1 01000 ..... 000 ..... 0100111 @r2 + #*** Vector AMO operations are encoded under the standard AMO major opcode *** vamoswapei8_v 00001 . . ..... ..... 000 ..... 0101111 @r_wdvm vamoswapei16_v 00001 . . ..... ..... 101 ..... 0101111 @r_wdvm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index fb6d092539..4274daf08e 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1030,6 +1030,67 @@ GEN_VEXT_TRANS(vle16ff_v, 16, 1, r2nfvm, ldff_op, ld_us_check) GEN_VEXT_TRANS(vle32ff_v, 32, 2, r2nfvm, ldff_op, ld_us_check) GEN_VEXT_TRANS(vle64ff_v, 64, 3, r2nfvm, ldff_op, ld_us_check) +/* + * load and store whole register instructions + */ +typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32); + +static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t data, + gen_helper_ldst_whole *fn, DisasContext *s, + bool is_store) +{ + TCGv_ptr dest; + TCGv base; + TCGv_i32 desc; + + dest = tcg_temp_new_ptr(); + base = tcg_temp_new(); + desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); + + gen_get_gpr(base, rs1); + tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); + + fn(dest, base, cpu_env, desc); + + tcg_temp_free_ptr(dest); + tcg_temp_free(base); + tcg_temp_free_i32(desc); + if (!is_store) { + mark_vs_dirty(s); + } + return true; +} + +/* + * load and store whole register instructions ignore vtype and vl setting. + * Thus, we don't need to check vill bit. (Section 7.9) + */ +#define GEN_LDST_WHOLE_TRANS(NAME, EEW, SEQ, ARGTYPE, ARG_NF, IS_STORE) \ +static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE * a) \ +{ \ + s->eew = EEW; \ + s->emul = (float)EEW / (1 << (s->sew + 3)) * s->flmul; \ + \ + if (!require_rvv(s)) { \ + return false; \ + } \ + \ + uint32_t data = 0; \ + bool ret; \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data = FIELD_DP32(data, VDATA, SEW, s->sew); \ + data = FIELD_DP32(data, VDATA, VTA, s->vta); \ + data = FIELD_DP32(data, VDATA, VMA, s->vma); \ + data = FIELD_DP32(data, VDATA, NF, ARG_NF); \ + ret = ldst_whole_trans(a->rd, a->rs1, data, gen_helper_##NAME, \ + s, IS_STORE); \ + return ret; \ +} + +GEN_LDST_WHOLE_TRANS(vl1r_v, 8, 0, vl1r_v, 1, false) + +GEN_LDST_WHOLE_TRANS(vs1r_v, 8, 1, vs1r_v, 1, true) + /* *** vector atomic operation */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index f49af084ef..995e873549 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -642,6 +642,53 @@ GEN_VEXT_LDFF(vle16ff_v, int16_t, lde_h, clearh) GEN_VEXT_LDFF(vle32ff_v, int32_t, lde_w, clearl) GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d, clearq) +/* + *** load and store whole register instructions + */ +static void +vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, + vext_ldst_elem_fn *ldst_elem, uint32_t esz, uintptr_t ra, + MMUAccessType access_type) +{ + uint32_t i, k; + uint32_t nf = vext_nf(desc); + uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3; + + /* probe every access */ + probe_pages(env, base, vlenb * nf * esz, ra, access_type); + + /* load bytes from guest memory */ + for (i = 0; i < vlenb; i++) { + k = 0; + while (k < nf) { + target_ulong addr = base + (i * nf + k) * esz; + ldst_elem(env, addr, i + k * vlmax, vd, ra); + k++; + } + } +} + +#define GEN_VEXT_LD_WHOLE(NAME, ETYPE, LOAD_FN) \ +void HELPER(NAME)(void *vd, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vext_ldst_whole(vd, base, env, desc, LOAD_FN, \ + sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \ +} + +GEN_VEXT_LD_WHOLE(vl1r_v, int8_t, lde_b) + +#define GEN_VEXT_ST_WHOLE(NAME, ETYPE, STORE_FN) \ +void HELPER(NAME)(void *vd, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vext_ldst_whole(vd, base, env, desc, STORE_FN, \ + sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \ +} + +GEN_VEXT_ST_WHOLE(vs1r_v, int8_t, ste_b) + /* *** Vector AMO Operations (Zvamo) */ -- 2.17.1