From: Frank Chang <frank.ch...@sifive.com>
Signed-off-by: Frank Chang <frank.ch...@sifive.com>
---
target/riscv/fpu_helper.c | 12 ++++++------
target/riscv/insn_trans/trans_rvv.inc.c | 18 +++++++++---------
target/riscv/internals.h | 9 +++++++++
3 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index bb346a82499..92e076c6ed8 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -55,23 +55,23 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t
rm)
{
int softrm;
- if (rm == 7) {
+ if (rm == FRM_DYN) {
rm = env->frm;
}
switch (rm) {
- case 0:
+ case FRM_RNE:
softrm = float_round_nearest_even;
break;
- case 1:
+ case FRM_RTZ:
softrm = float_round_to_zero;
break;
- case 2:
+ case FRM_RDN:
softrm = float_round_down;
break;
- case 3:
+ case FRM_RUP:
softrm = float_round_up;
break;
- case 4:
+ case FRM_RMM:
softrm = float_round_ties_away;
break;
default:
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index f2bd3972558..6cdb1659b59 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2418,7 +2418,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##NAME##_d, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2498,7 +2498,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##NAME##_w, \
gen_helper_##NAME##_d, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2530,7 +2530,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2566,7 +2566,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
static gen_helper_opfvf *const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2596,7 +2596,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2632,7 +2632,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
static gen_helper_opfvf *const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2709,7 +2709,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
gen_helper_##NAME##_d, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2850,7 +2850,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2896,7 +2896,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 4fb683a7399..97f023361a9 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -38,6 +38,15 @@ target_ulong fclass_d(uint64_t frs1);
#define SEW32 2
#define SEW64 3
+enum {
+ FRM_RNE = 0, /* Round to Nearest, ties to Even */
+ FRM_RTZ = 1, /* Round towards Zero */
+ FRM_RDN = 2, /* Round Down */
+ FRM_RUP = 3, /* Round Up */
+ FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */
+ FRM_DYN = 7, /* Dynamic rounding mode */
+};
+
static inline uint64_t nanbox_s(float32 f)
{
return f | MAKE_64BIT_MASK(32, 32);
--
2.17.1
