On Thursday, August 13, 2020, Kaige Li <lika...@loongson.cn> wrote:
> This will help ensure that style guidelines are being maintained during
> subsequent changes.
>
> Signed-off-by: Kaige Li <lika...@loongson.cn>
> ---
Agreed.
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.de...@gmail.com>
> target/mips/translate_init.inc.c | 61 ++++++++++++++++++++----------
> ----------
> 1 file changed, 31 insertions(+), 30 deletions(-)
>
> diff --git a/target/mips/translate_init.inc.c
> b/target/mips/translate_init.inc.c
> index 637cacc..0740819 100644
> --- a/target/mips/translate_init.inc.c
> +++ b/target/mips/translate_init.inc.c
> @@ -53,8 +53,7 @@
>
> /***********************************************************
> ******************/
> /* MIPS CPU definitions */
> -const mips_def_t mips_defs[] =
> -{
> +const mips_def_t mips_defs[] = {
> {
> .name = "4Kc",
> .CP0_PRid = 0x00018000,
> @@ -766,8 +765,8 @@ const mips_def_t mips_defs[] =
> .name = "Loongson-2E",
> .CP0_PRid = 0x6302,
> /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.
> */
> - .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
> - (0x1<<5) | (0x1<<4) | (0x1<<1),
> + .CP0_Config0 = (0x1 << 17) | (0x1 << 16) | (0x1 << 11) | (0x1 <<
> 8) |
> + (0x1 << 5) | (0x1 << 4) | (0x1 << 1),
> /* Note: Config1 is only used internally,
> Loongson-2E has only Config0. */
> .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
> @@ -786,8 +785,8 @@ const mips_def_t mips_defs[] =
> .name = "Loongson-2F",
> .CP0_PRid = 0x6303,
> /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.
> */
> - .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
> - (0x1<<5) | (0x1<<4) | (0x1<<1),
> + .CP0_Config0 = (0x1 << 17) | (0x1 << 16) | (0x1 << 11) | (0x1 <<
> 8) |
> + (0x1 << 5) | (0x1 << 4) | (0x1 << 1),
> /* Note: Config1 is only used internally,
> Loongson-2F has only Config0. */
> .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
> @@ -932,19 +931,19 @@ void mips_cpu_list(void)
> }
>
> #ifndef CONFIG_USER_ONLY
> -static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
> +static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def)
> {
> env->tlb->nb_tlb = 1;
> env->tlb->map_address = &no_mmu_map_address;
> }
>
> -static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
> +static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def)
> {
> env->tlb->nb_tlb = 1;
> env->tlb->map_address = &fixed_mmu_map_address;
> }
>
> -static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
> +static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
> {
> env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
> env->tlb->map_address = &r4k_map_address;
> @@ -956,40 +955,41 @@ static void r4k_mmu_init (CPUMIPSState *env, const
> mips_def_t *def)
> env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
> }
>
> -static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
> +static void mmu_init(CPUMIPSState *env, const mips_def_t *def)
> {
> env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
>
> switch (def->mmu_type) {
> - case MMU_TYPE_NONE:
> - no_mmu_init(env, def);
> - break;
> - case MMU_TYPE_R4000:
> - r4k_mmu_init(env, def);
> - break;
> - case MMU_TYPE_FMT:
> - fixed_mmu_init(env, def);
> - break;
> - case MMU_TYPE_R3000:
> - case MMU_TYPE_R6000:
> - case MMU_TYPE_R8000:
> - default:
> - cpu_abort(env_cpu(env), "MMU type not supported\n");
> + case MMU_TYPE_NONE:
> + no_mmu_init(env, def);
> + break;
> + case MMU_TYPE_R4000:
> + r4k_mmu_init(env, def);
> + break;
> + case MMU_TYPE_FMT:
> + fixed_mmu_init(env, def);
> + break;
> + case MMU_TYPE_R3000:
> + case MMU_TYPE_R6000:
> + case MMU_TYPE_R8000:
> + default:
> + cpu_abort(env_cpu(env), "MMU type not supported\n");
> }
> }
> #endif /* CONFIG_USER_ONLY */
>
> -static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
> +static void fpu_init(CPUMIPSState *env, const mips_def_t *def)
> {
> int i;
>
> - for (i = 0; i < MIPS_FPU_MAX; i++)
> + for (i = 0; i < MIPS_FPU_MAX; i++) {
> env->fpus[i].fcr0 = def->CP1_fcr0;
> + }
>
> memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
> }
>
> -static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
> +static void mvp_init(CPUMIPSState *env, const mips_def_t *def)
> {
> env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
>
> @@ -999,9 +999,10 @@ static void mvp_init (CPUMIPSState *env, const
> mips_def_t *def)
> implemented, 5 TCs implemented. */
> env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
> (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
> -// TODO: actually do 2 VPEs.
> -// (1 << CP0MVPC0_TCA) | (0x1 <<
> CP0MVPC0_PVPE) |
> -// (0x04 << CP0MVPC0_PTC);
> +/* TODO: actually do 2 VPEs.
> + * (1 << CP0MVPC0_TCA) | (0x1 <<
> CP0MVPC0_PVPE) |
> + * (0x04 << CP0MVPC0_PTC);
> + */
> (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE)
> |
> (0x00 << CP0MVPC0_PTC);
> #if !defined(CONFIG_USER_ONLY)
> --
> 2.1.0
>
>
